Series/parallel/series shift register memory comprising redundant parallel-connected storage registers, and display apparatus comprising a picture memory thus organized

Claim 1

A series-parallel-series shift register memory comprising: a serial data input (200) for first electrical signals having a value range of at least two values; a redundancy generator (202, 204) fed by said serial data input for generating, on the basis of a plurality of p successive first electrical signals, (n-p) greater than or equal to one redundant electrical signal; a converter (22) fed by said redundancy generator for receiving said p first electrical signals and thereafter said (n-p) redundant electrical signals and converting each of these electrical signals into a series of p data representations; and a substrate comprising storage positions for the storage of a data representation as represented by a single physical quantity in that storage position; said substrate having a serial input register (206) fed by said converter; a plurality of parallel storage registers (208) fed in parallel by parallel outputs of said serial input register; and a serial output register (210) fed in parallel by the output of each of said storage registers; and comprising: a serial data output (32), wherein said storage registers comprise first storage registers for transiently storing data representations of said first electrical signals in series of equal lengths of m>2 storage positions each; and second storage registers for transiently storing data representations of said redundant electrical signals in a second series of equal lengths of 1<t≦(m-1) storage positions each; said shift register memory having a transfer control device for transferring these representations in parallel to the storage registers after introduction of n data representations in the input register and at the same time transferring n data representations from the storage registers to the output register; said transfer control otherwise activating only the input/and output registers, whereby the storage length of said first storage registers is longer than the storage length of said second storage registers; said shift register memory furthermore comprising a second converter (34) fed by said serial data output for reconstituting electrical signals from data representations received; and a redundancy reducer (212, 214) fed by said second converter for receiving first said (n-p) redundant signals and thereafter said p first electrical signals and thereby correcting at least one deficient electrical signal within said p first electrical signals for outputting said p first electrical signals on a serial data output (230) element.