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US4563593A Expired / Lapsed US ⏱️ 0.0 years remaining

Transition detector circuit

Assignee: Toshiba Corp
•
Filing: 1983-10-03
•
Granted: 1986-01-07
•
Expires: 2003-10-03
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Abstract

Abstract A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal. The transition detector circuit further comprises a first switching circuit which turns on or off in response to a signal fed from the third invertor train to produce a pulse signal having a first delay time determined by the first and third invertor trains, and a second switching circuit which turns on or off in response to a signal fed from the fourth invertor train and turns off or on in response to a signal fed from the fifth invertor train to produce a pulse signal having a second delay time determined by the second, fourth and fifth invertor trains.

Inventors

  • 👤 Mitsuo Isobe
  • 👤 Takayuki Ohtani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:44
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534; H03K3/00; H03K3/02

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 247 words
A transition detector circuit comprising: (a) a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal; (b) a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to said signal input terminal, while the output thereof is connected to an antiphase output terminal; (c) a third invertor train, comprising at least one stage of an invertor, connected to the output of said first invertor train; (d) a fourth invertor train, comprising at least one stage of an invertor, connected to the output of said second invertor train; (e) a fifth invertor train, comprising at least one stage of an invertor, connected to said signal input terminal; (f) a first switching circuit which turns on or off in response to a signal fed from said signal input terminal and turns off or on in response to a signal fed from said third invertor train to produce a pulse signal having a first delay time determined by said first and third invertor trains; and (g) a second switching circuit which turns on or off in response to a signal fed from said fourth invertor train and turns off or on in response to a signal fed from said fifth invertor train to produce a pulse signal having a second delay time determined by said second, fourth and fifth invertor trains.
Claim 2
Dependent Claim 247 words
A transition detector circuit comprising: (a) a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal; (b) a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to said signal input terminal, while the output thereof is connected to an antiphase output terminal; (c) a third invertor train, comprising at least one stage of an invertor, connected to the output of said first invertor train; (d) a fourth invertor train, comprising at least one stage of an invertor, connected to the output of said second invertor train; (e) a fifth invertor train, comprising at least one stage of an invertor, connected to said signal input terminal; (f) a first switching circuit which turns on or off in response to a signal fed from said signal input terminal and turns off or on in response to a signal fed from said third invertor train to produce a pulse signal having a first delay time determined by said first and third invertor trains; and (g) a second switching circuit which turns on or off in response to a signal fed from said fourth invertor train and turns off or on in response to a signal fed from said fifth invertor train to produce a pulse signal having a second delay time determined by said second, fourth and fifth invertor trains.
Claim 3
Dependent Claim 96 words
A transition detector circuit as defined in claim 1, wherein the following relationship holds V.sub.3 >V.sub.1 >V.sub.2 >V.sub.4, where V 1 denotes a threshold voltage of a first stage of an invertor of said first invertor train, V 2 a threshold voltage of a first stage of an invertor of said second invertor train, V 3 a threshold voltage of a first stage of said fifth invertor train, and V 4 a voltage at a time when said first switching circuit turns on or off in response to a signal fed from said signal input terminal.
Claim 4
Dependent Claim 38 words
A transition detector circuit as defined in claim 2, wherein the relationship in connection with the threshold voltages is formed by suitably selecting the dimension of channels of transistor constituting each of said invertors and said switching circuits.

References Cited (Backward Citations)

US3805170A Cited
US3678295A Cited
US3942037A Cited
US4039858A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-01-06 1989-07-08 1990-01-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-01-06 1993-07-08 1994-01-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-01-06 1997-07-08 1998-01-07 $7700.00 Window Closed / Lapsed

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