Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
221 words
A clock signal recovery system for TDMA satellite communication system in which a transmitting earth station transmits periodically modulated burst signals which are synchronized with each other in both frequency and phase and a receiving earth station demodulates that burst signal by using the recovered clock signal comprising: an input terminal for receiving TDMA bust signals; a burst clock recovery means to obtain burst clock from the received burst signal; a clock control means to generate the recovered clock by controlling a local clock oscillator according to stored frequency and/or phase information and said burst clock, a frequency and/or phase memory means for storing frequency and/or phase information of an output of said clock control means for more than two frame periods, said frequency and/or phase memory means including a processor means for providing a signal of the average of the frequencies and/or phase information stored in memory, a decision circuit for regenerating received burst signal by using the recovered clock signal, a first output terminal coupled with output of said decision circuit to provide regenerated burst signal, a synchronization detection circuit coupled with said output terminal for indicating establishment of clock synchronization of a clock signal after receiving predetermined pluality of bursts from the same transmitting earth station, a second output terminal coupled with output of said synchronization detection circuit.
Claim 2
Dependent Claim
221 words
A clock signal recovery system for TDMA satellite communication system in which a transmitting earth station transmits periodically modulated burst signals which are synchronized with each other in both frequency and phase and a receiving earth station demodulates that burst signal by using the recovered clock signal comprising: an input terminal for receiving TDMA bust signals; a burst clock recovery means to obtain burst clock from the received burst signal; a clock control means to generate the recovered clock by controlling a local clock oscillator according to stored frequency and/or phase information and said burst clock, a frequency and/or phase memory means for storing frequency and/or phase information of an output of said clock control means for more than two frame periods, said frequency and/or phase memory means including a processor means for providing a signal of the average of the frequencies and/or phase information stored in memory, a decision circuit for regenerating received burst signal by using the recovered clock signal, a first output terminal coupled with output of said decision circuit to provide regenerated burst signal, a synchronization detection circuit coupled with said output terminal for indicating establishment of clock synchronization of a clock signal after receiving predetermined pluality of bursts from the same transmitting earth station, a second output terminal coupled with output of said synchronization detection circuit.
Claim 3
Dependent Claim
42 words
A clock signal recovery system according to claim 1, wherein said clock control means is controlled by output of said frequency and/or phase memory means, and said decision circuit uses the output of said clock control means for regenerating the received bursts.
Claim 4
Dependent Claim
31 words
A clock signal recovery system according to claim 1, wherein said decision circuit takes the output of said frequency and/or phase memory means through a shifter for regenerating the received bursts.
Claim 5
Dependent Claim
31 words
A clock signal recovery system according to claim 1, wherein said frequency and/or phase memory means provides a moving average of frequency and/or phase informations of more than two preceding bursts.
Claim 6
Dependent Claim
53 words
A clock signal recovery system according to claim 1, wherein said frequency and/or phase memory means is implemented by a processor which controls shift means for providing a recovered clock signal, and said shift means shifts a timing signal which is controlled by a received burst signal to provide a synchronized clock signal.
Claim 7
Dependent Claim
50 words
A clock signal recovery system according to claim 1, wherein said synchronization detection circuit has a plurality of counters for counting unique word in a frame for every transmitting earth station, and provides synchronization establishment output signal for each transmitting earth station when predetermined number of unique words are received.