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US4560918A Expired / Lapsed US ⏱️ 0.0 years remaining

High-efficiency, low-voltage-drop series regulator using as its pass element an enhancement-mode FET with boosted gate voltage

Assignee: Lockheed Martin Corp
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Filing: 1984-04-02
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Granted: 1985-12-24
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Expires: 2004-04-02
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Abstract

Abstract A highly efficient series regulator for use where output voltage may closely approach input voltage uses the channel of a field effect transistor as a series voltage-dropping element. The conduction of the channel of the field effect transistor is controlled without consumption of appreciable power in the control circuitry for the transistor. Presently available power field effect transistors are of p-channel enhancement mode type. Their threshold voltages are sufficiently high as to make difficult the closing a d.c. feedback loop as will allow output voltage to approach closely input voltage. This problem of closing the d.c. feedback loop is overcome by using voltage boost circuitry, powered from the input voltage supply to the regulator, against which to refer the error signal applied to the gate electrode of the field effect transistor.

Inventors

  • 👤 Patrick J. Callen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 10:22
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/575

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 171 words
A series regulator comprising: common and input terminals for receiving an applied input voltage; an output terminal for supplying an output level which is to be regulated to a prescribed value; at least one field effect transistor, having a channel connected between said input and output terminals, and having a gate electrode between which and said common terminal a voltage must appear that is larger than said input voltage applied between said input terminal and said common terminal, in order to control the conduction of said channel as output voltage approaches the input voltage in value, which gate electrode connects to a control voltage node; a voltage boost circuit for developing from the input voltage appearing between said common and input terminals a larger voltage as referred to said common terminal; means responsive to the amount said output level exceeds said prescribed value therefor for developing said error signal voltage as a voltage drop from said larger voltage; and means for applying said error signal voltage to said control voltage node.
Claim 2
Dependent Claim 171 words
A series regulator comprising: common and input terminals for receiving an applied input voltage; an output terminal for supplying an output level which is to be regulated to a prescribed value; at least one field effect transistor, having a channel connected between said input and output terminals, and having a gate electrode between which and said common terminal a voltage must appear that is larger than said input voltage applied between said input terminal and said common terminal, in order to control the conduction of said channel as output voltage approaches the input voltage in value, which gate electrode connects to a control voltage node; a voltage boost circuit for developing from the input voltage appearing between said common and input terminals a larger voltage as referred to said common terminal; means responsive to the amount said output level exceeds said prescribed value therefor for developing said error signal voltage as a voltage drop from said larger voltage; and means for applying said error signal voltage to said control voltage node.

References Cited (Backward Citations)

US2984779A Cited
DE2118428A1 Cited
US4291266A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-12-23 1989-06-24 1989-12-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-12-23 1993-06-24 1993-12-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-12-23 1997-06-24 1997-12-24 $7700.00 Window Closed / Lapsed

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