Arrangement of a dynamic random access memory

Claim 1

An arrangement of a high-capacity dynamic random access memory for use in a video circuit having a pick-up unit for scanning lines of picture elements according to interlaced scanning method, and a receiving unit having two interchangeable monitors of different resolutions, said arrangement comprising a plurality of RAM segments, the number of which is determined by the number of gradations of picture elements; each segment including a plurality of consecutively arranged RAM chips the number of which is determined by a minimum read/write cycle time and by a scanning cycle time; each RAM chip including n×n×l memory locations arranged in address lines and address columns whereby the memory locations in each segment being simultaneously addressable; means for writing/reading binary signals pertaining to odd-numbered picture-element lines into one half of address columns of each RAM segment and means for writing/reading binary signals pertaining to even-numbered picture-element lines into another half of columns in the RAM segment; control means assigned to respective halves of each segment for writing/reading into consecutive pairs of adjoining columns of storing locations sets of binary signals pertaining to corresponding video lines in each half in such a manner that the consecutively stored sets of signals in adjoining pairs of columns are arranged in pairs side by side and one below the other; and means for switching over the read-out operation to retrieve the stored information from one of the adjoining columns in respective pairs while jumping over the other column.