Signal processing circuit

Claim 2

A signal processing circuit comprising: a power supply voltage line, a reference voltage line and a constant voltage terminal; a signal input terminal and a signal output terminal; a differential amplifying circuit for generating first and second output signals from first and second output terminals, first and second input terminals of said differential amplifying circuit being respectively coupled to said signal input terminal and constant voltage terminal; a first current mirror circuit having an input current path coupled between the first output terminal of said differential amplifying circuit and said power supply voltage line, and first and second output current paths which are each coupled at one end to said power supply voltage line; a second current mirror circuit having an input current path coupled between the second output terminal of said differential amplifying circuit and said power supply voltage line, a first output current path coupled between said signal input terminal and the power supply voltage line, and a second output current path coupled between said signal output terminal and the power supply voltage line; a third current mirror circuit having an input current path coupled between the other end of the first output current path of said first current mirror circuit and said reference voltage line, and an output current path coupled between said signal input terminal and the reference voltage line; and a fourth current mirror circuit having an input current path coupled between the other end of the second output current path of said first current mirror circuit and said reference voltage line, and an output current path coupled between said signal output terminal and the reference voltage line.

Claim 3

A signal processing circuit according to claim 1, wherein said differential amplifying circuit comprises: constant current source means; and first and second transistors of the same conductivity type whose bases are respectively coupled to said signal input terminal and constant voltage terminal and whose emitters are together coupled to said reference voltage line through said constant current source means.

Claim 4

A signal processing circuit according to claim 2, wherein said differential amplifying circuit further has resistors coupled respectively to the emitters of said first and second transistors.

Claim 5

A signal processing circuit according to claim 2, wherein said differential amplifying circuit further has a resistor coupled between the emitters of said first and second transistors, and said constant current source means has first and second constant current sources coupled to the emitters of said first and second transistors.

Claim 6

A signal processing circuit according to claim 2, wherein said first current mirror circuit comprises a third transistor whose collector is coupled to the collector of said first transistor and whose emitter is coupled to said power supply voltage line and whose base is coupled to the collector thereof, and fourth and fifth transistors whose emitters are coupled to the power supply voltage line and whose bases are coupled to the base of said third transistor, said second current mirror circuit comprises a sixth transistor whose emitter and collector are respectively coupled to said power supply voltage line and to the collector of said second transistor and whose base is coupled to the collector thereof, a seventh transistor whose current path is coupled between said power supply voltage line and said signal input terminal and whose base is coupled to the base of said sixth transistor, and an eighth transistor whose current path is coupled between said power supply voltage line and said signal output terminal and whose base is coupled to the base of said sixth transistor, said third current mirror circuit comprises a ninth transistor whose base and collector are coupled to the collector of said fourth transistor and whose emitter is coupled to said reference voltage line, and a tenth transistor whose current path is coupled between said signal input terminal and said reference voltage line and whose base is coupled to the base of said ninth transistor, and said fourth current mirror circuit comprises an eleventh transistor whose base and collector are coupled to the collector of said fifth transistor and whose emitter is coupled to said reference voltage line, and a twelfth transistor whose current path is coupled between said signal output terminal and the reference voltage line and whose base is coupled to the base of said eleventh transistor.

Claim 7

A signal processing circuit according to claim 5, wherein said first, second and ninth to twelfth transistors are npn transistors, and said third to eighth transistors are pnp transistors.

Claim 8

A signal processing circuit according to claim 6, further comprising resistive means connected between said signal output terminal and constant voltage terminal.

Claim 9

A signal processing circuit according to claim 6, further comprising resistive means connected between said signal output terminal and the collectors of said eighth and twelfth transistors and an operational amplifier whose inverting input terminal is connected to the collectors of said eighth and twelfth transistors, whose non-inverting input terminal is connected to said constant voltage terminal and whose output terminal is connected to said signal output terminal.

Claim 10

A signal processing circuit comprising: a power supply voltage line, a reference voltage line and a constant voltage terminal; a signal input terminal and a signal output terminal; a differential amplifying circuit for generating first and second output signals from first and second output terminals, first and second input terminals of said differential amplifying circuit being respectively coupled to said signal input terminal and constant voltage terminal; a first current mirror circuit having an input current path coupled between the first output terminal of said differential amplifying circuit and said power supply voltage line, a first output current path one end of which is coupled to said power supply voltage line, and second output current path coupled between said signal output terminal and said power supply voltage line; a second current mirror circuit having an input current path coupled between the second output terminal of said differential amplifying circuit and said power supply voltage line, a first output current path coupled between said signal input terminal and the power supply voltage line, and a second output current path one end of which is coupled to said power supply voltage line; a third current mirror circuit having an input current path coupled between the other end of the first output current path of said first current mirror circuit and said reference voltage line, and an output current path coupled between said signal input terminal and the reference voltage line; and a fourth current mirror circuit having an input current path coupled between the other end of the second output current path of said second current mirror circuit and said reference voltage line, and an output current path coupled between said signal output terminal and the reference voltage line.

Claim 11

A signal processing circuit comprising: a power supply voltage line, a reference voltage line and a constant voltage terminal; a signal input terminal and a signal output terminal; a differential amplifying circuit for generating first and second output signals from first and second output terminals, first and second input terminals of said differential amplifying circuit being respectively coupled to said signal input terminal and constant voltage terminal; a first current mirror circuit having an input current path coupled between the first output terminal of said differential amplifying circuit and said power supply voltage line, a first output current path one end of which is coupled to said power supply voltage line, and second output current path coupled between said signal output terminal and said power supply voltage line; a second current mirror circuit having an input current path coupled between the second output terminal of said differential amplifying circuit and said power supply voltage line, a first output current path coupled between said signal input terminal and the power supply voltage line, and a second output current path one end of which is coupled to said power supply voltage line; a third current mirror circuit having an input current path coupled between the other end of the first output current path of said first current mirror circuit and said reference voltage line, and an output current path coupled between said signal input terminal and the reference voltage line; and a fourth current mirror circuit having an input current path coupled between the other end of the second output current path of said second current mirror circuit and said reference voltage line, and an output current path coupled between said signal output terminal and the reference voltage line.

Claim 12

A signal processing circuit according to claim 9, wherein said differential amplifying circuit comprises: constant current source means; and first and second transistors of the same conductivity type whose bases are respectively coupled to said signal input terminal and constant voltage terminal and whose emitters are together coupled to said reference voltage line through said constant current source means.

Claim 13

A signal processing circuit according to claim 10, wherein said differential amplifying circuit further has resistors coupled respectively to the emitters of said first and second transistors.

Claim 14

A signal processing circuit according to claim 10, wherein said differential amplifying circuit further has a resistor coupled between the emitters of said first and second transistors, and said constant current source means has first and second constant current sources coupled to the emitters of said first and second transistors.

Claim 15

A signal processing circuit according to claim 10, wherein said first current mirror circuit comprises a third transistor whose collector is coupled to the collector of said first transistor and whose emitter is coupled to said power supply voltage line and whose base is coupled to the collector thereof, and fourth and fifth transistors whose emitters are coupled to the power supply voltage line and whose bases are coupled to the base of the third transistor. said second current mirror circuit comprises a sixth transistor whose emitter and collector are respectively coupled to said power supply voltage line and to the collector of said second transistor and whose base is coupled to the collector thereof, and seventh transistor whose current path is coupled between said power supply voltage line and the signal input terminal and whose base is coupled to the base of said sixth transistor, and an eighth transistor whose current path is coupled between the power supply voltage line and the signal output terminal and whose base is coupled to the base of said sixth transistor, said third current mirror circuit comprises a ninth transistor whose base and collector are coupled to the collector of said fourth transistor and whose emitter is coupled to said reference voltage line and a tenth transistor whose current path is coupled between the signal input terminal and the reference voltage line and whose base is coupled to the base of the ninth transistor, and said fourth current mirror circuit comprises an eleventh transistor whose base and collector are coupled to the collector of said eighth transistor and whose emitter is coupled to the reference voltage line, and a twelfth transistor whose current path is coupled between said signal output terminal and said reference voltage line and whose base is coupled to the base of the eleventh transistor.

Claim 16

A signal processing circuit according to claim 13, wherein said first, second and ninth to twelfth transistors are npn transistors, and said third to eighth transistors are pnp transistors.

Claim 17

A signal processing circuit according to claim 13, wherein said fifth and eighth transistors are double emitter transistors.

Claim 18

A signal processing circuit according to claim 13, wherein said third and sixth transistors are multi-emitter transistors.