US4558283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for generating a sum or differential frequency signal
Assignee: Sony Corp
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Filing: 1984-02-08
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Granted: 1985-12-10
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Expires: 2004-02-08
Abstract
Abstract There is provided a sum or differential frequency signal generating circuit for two input signals of first and second frequencies. This circuit comprises: 1st and 2nd differential amplifiers which receive the input signal of the 1st frequency and generate differential 1st and 2nd output currents having the phase difference of 90°; 3rd and 4th differential amplifiers which receive the input signal of the 2nd frequency and generate differential 3rd and 4th output currents having the phase difference of 90°; a 1st multiplier consisting of a differential amplifier for generating the multiplication output current of the output currents of the 1st and 3rd differential amplifiers; a 2nd multiplier consisting of a differential amplifier for generating the multiplication output current of the output currents of the 2nd and 4th differential amplifiers; and an output terminal at which the output currents of the 1st and 2nd multipliers are synthesized and fetched. This signal generating circuit hardly needs adjusting circuit but can suppress unnecessary signal components and is suitable for making an IC and can be applied to an SSB modulator and other similar circuits.
Inventors
- 👤 Kazuo Yamagiwa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:51
CPC Classifications
H; H03; H03B; H03B21/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
A sum or differential frequency signal generating circuit to which input signals of first and second frequencies are supplied and which generates an output signal of the frequency of the sum or difference of said first and second frequencies, said signal generating circuit comprising: first and second differential amplifiers to which the input signal of said first frequency is supplied and which generate differential first and second output currents having a phase difference of 90° with each other; third and fourth differential amplifiers to which the input signal of said second frequency is supplied and which generate differential third and fourth output currents having a phase difference of 90° with each other; a first multiplier, constituted by a differential amplifier, for generating the multiplication output current of the output currents of said first and third differential amplifiers; a second multiplier, constituted by a differential amplifier, for generating the multiplication output current of the output currents of said second and fourth differential amplifiers; and an output terminal at which the output currents of said first and second multipliers are synthesized and fetched.
Claim 2
Dependent Claim
181 words
A sum or differential frequency signal generating circuit to which input signals of first and second frequencies are supplied and which generates an output signal of the frequency of the sum or difference of said first and second frequencies, said signal generating circuit comprising: first and second differential amplifiers to which the input signal of said first frequency is supplied and which generate differential first and second output currents having a phase difference of 90° with each other; third and fourth differential amplifiers to which the input signal of said second frequency is supplied and which generate differential third and fourth output currents having a phase difference of 90° with each other; a first multiplier, constituted by a differential amplifier, for generating the multiplication output current of the output currents of said first and third differential amplifiers; a second multiplier, constituted by a differential amplifier, for generating the multiplication output current of the output currents of said second and fourth differential amplifiers; and an output terminal at which the output currents of said first and second multipliers are synthesized and fetched.
Claim 3
Dependent Claim
34 words
A sum or differential frequency signal generating circuit according to claim 1, wherein a gain control circuit is provided for at least one differential amplifier of said first, second, third or fourth differential amplifier.
Claim 4
Dependent Claim
45 words
A sum or differential frequency signal generating circuit according to claim 1, wherein a resistor and a capacitor are respectively inserted in the loop current line of said first and second differential amplifiers, thereby generating a differential output current having a phase difference of 90°.
Claim 5
Dependent Claim
45 words
A sum or differential frequency signal generating circuit according to claim 1, wherein a resistor and a capacitor are respectively inserted in the loop current line of said third and fourth differential amplifiers, thereby generating a differential output current having a phase difference of 90°.
Claim 6
Dependent Claim
104 words
A sum or differential frequency signal generating circuit according to claim 1, wherein the base of one transistor of said first differential amplifier and the base of one transistor of said second differential amplifier are connected and a series circuit consisting of a resistor and a capacitor is interposed between the base of the other transistor of the first differential amplifier and the base of the other transistor of the second differential amplifier, and wherein the connecting point of said resistor and said capacitor and the base connecting point of said transistors are connected, thereby adding said first input signal to said series circuit.
Claim 7
Dependent Claim
104 words
A sum or differential frequency signal generating circuit according to claim 1, wherein the base of one transistor of said third differential amplifier and the base of one transistor of said fourth differential amplifier are connected and a series circuit consisting of a resistor and a capacitor is interposed between the base of the other transistor of the third differential amplifier and the base of the other transistor of the fourth differential amplifier, and wherein the connecting point of said resistor and said capacitor and the base connecting point of said transistors are connected, thereby adding said second input signal to said series circuit.
Claim 8
Dependent Claim
42 words
A sum or differential frequency signal generating circuit according to claim 4, wherein a fifth differential amplifier is connected in parallel to said first differential amplifier and the DC balance of the first differential amplifier is kept by said fifth differential amplifier.
Claim 9
Dependent Claim
42 words
A sum or differential frequency signal generating circuit according to claim 4, wherein a sixth differential amplifier is connected in parallel to said third differential amplifier and the DC balance of the third differential amplifier is kept by said sixth differential amplifier.
Claim 10
Dependent Claim
42 words
A sum or differential frequency signal generatoing circuit according to claim 5, wherein a fifth differential amplifier is connected in parallel to said first differential amplifier and the DC balance of the first differential amplifier is kept by said fifth differential amplifier.
Claim 11
Dependent Claim
42 words
A sum or differential frequency signal generating circuit according to claim 6, wherein a sixth differential amplifier is connected in parallel to said third differential amplifier and the DC balance of the third differential amplifier is kept by said sixth differential amplifier.
References Cited (Backward Citations)
US3568067A
Cited
US4308471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-09 | 1989-06-10 | 1989-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-09 | 1993-06-10 | 1993-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-09 | 1997-06-10 | 1997-12-10 | $7700.00 | Window Closed / Lapsed |