Power line carrier FSK data system

Claim 1

A data communication system for communicating data between a first and a second location over an electrical power line which also carries alternating current electrical power having a frequency f PC , the system comprising: transmitter means at the first location for providing to the power line a periodic frequency shift keyed (FSK) signal representing a serial input stream of binary bits, the FSK signal having a frequency f FSK and a predetermined data rate, wherein f FSK is greater than the data rate, and the date rate is greater than f PC , the transmitter means comprising: first means for deriving from the power line a signal having frequency f PC ; first phase locked loop means locked to the signal having frequency f PC for synthesizing the FSK signal and a transmitter timing signal which determines the data rate, wherein the first phase locked loop means comprises: first oscillator means for producing the FSK signal with a frequency f FSK which is a function of a first control signal and a second control signal; divider means for dividing the FSK signal to produce a synthesized signal having a frequency f SPC which is equal to f PC when the first phase locked loop means is in lock and to produce the transmitter timing signal which defines a bit time period for each bit of the serial input stream; first phase detector means for providing a first phase detector output which is a function of a phase comparison of the signal having frequency f PC and the synthesized signal having frequency f SPC ; and means for providing the first control signal as a function of the first phase detector output; control means for providing the second control signal during each bit time period which causes the first oscillator means to produce the FSK signal with a frequency f FSK which is greater than a reference frequency f O to represent a bit of the input stream having first binary state and is less than f O to represent a bit of the input stream having a second binary state; means for superimposing the FSK signal onto the power line; and receiver means at the second location for providing a periodic serial output stream of binary bits, the receiver means comprising: second means for deriving from the power line a signal having frequency f PC ; second phase locked loop means locked to the signal having frequency f PC for synthesizing a reference signal having frequency f O and a receiver timing signal which determines the data rate, wherein the second phase locked loop means comprises: second oscillator means for producing the reference signal with a frequency f O which is a function of a control signal; divider means for dividing the reference signal to produce a synthesized signal having a frequency f SPC which is equal to f PC when the second phase locked loop means is in lock and to produce a receiver timing signal which defines a bit time period for each bit of the serial output stream; second phase detector means for providing a second phase detector output which is a function of a phase comparison of the signal having frequency f PC and the signal having frequency f SPC ; and means for providing the control signal to the second oscillator means as a function of the second phase detector output; means for deriving the FSK signal from the power line; and frequency discriminator means responsive to the receiver timing signal for providing the periodic serial output stream of binary bits as a function of periodic comparison of the FSK signal and the reference signal.