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US4555705A Expired / Lapsed US ⏱️ 0.0 years remaining

System for providing a summarized information on the line spectrum from a Doppler radar spectrum analyzer

Assignee: International Standard Electric Corp
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Filing: 1982-11-19
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Granted: 1985-11-26
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Expires: 2002-11-19
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Abstract

Abstract A device providing summarized information from the digital spectrum analyzer output within a Doppler radar. Four memories, each of 256 word capacity, are included. Each of said memories is addressed by a group of eight bits among the sixteen bits provided by the spectrum analyzer and a logic circuit reconstitutes an elementary summary plot from the contents of said four memories. For a sixteen-line spectrum analyzer it is thus possible to replace a read-only memory for 64K, seven-bit words by the aforementioned four such read-only memories each of 256, seven-bit words.

Inventors

  • 👤 Jean-Louis G. Bossennec
  • 👤 Jean-Claude A. Debuisser
  • 👤 Philippe F. Farhi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 08:43
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/50; G01S13/52; G01S13/522; G01S13/524; G01S13/5246

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 324 words
A Doppler radar plot summarizer for moving targets supplying a digital signal for one or more targets, said signal for each target range called an elementary summary plot, PRE, corresponding to a given delay of the received signal, said digital signal consisting of one target detection bit D, one bit V indicating whether the target is a single-speed target and one word of m+1 bits containing information on the speed of that target, if the target is of a single speed, wherein said plot summarizer receives a digital signal called an elementary raw plot, PBE, from a circuit comprising in series a 2 m point spectrum analyser, made up of a weighting circuit, a 2 m Fourier transform calculator and a modulus extractor, and a contrast detector furnishing, for each of these target ranges, said elementary raw plot consisting of one word of 2 m bits, the weighting performed by said weighting circuit being such that it limits the maximum number of cyclically contiguous lines for which a single-speed target is detected to 2 m /4+1, said plot summarizer comprising: four read-only memories respectively addressed by a first, a second, a third and a fourth group of bits of said elementary raw plot and providing at their outputs corresponding digital signals of m+3 bits called pseudosummaries, said first group consisting of bits 0 to 2 m-1 -1 of the elementary raw plot, said second group consisting of bits 2 m-2 to 2 m-1 + 2 m-2 -1 of the elementary raw plot, said third group, complementary to said first group, consisting of bits 2 m-1 to 2 m -1 of the elementary raw plot and said fourth group, complementary to said second group, consisting of bits 2 m-1 +2 m-2 to 2 m -1 and 0 to 2 m-2 -1 of the elementary raw plot; and a logic circuit for reconstituting said elementary summary plot from said pseudosummaries provided by said four read-only memories.
Claim 2
Dependent Claim 324 words
A Doppler radar plot summarizer for moving targets supplying a digital signal for one or more targets, said signal for each target range called an elementary summary plot, PRE, corresponding to a given delay of the received signal, said digital signal consisting of one target detection bit D, one bit V indicating whether the target is a single-speed target and one word of m+1 bits containing information on the speed of that target, if the target is of a single speed, wherein said plot summarizer receives a digital signal called an elementary raw plot, PBE, from a circuit comprising in series a 2 m point spectrum analyser, made up of a weighting circuit, a 2 m Fourier transform calculator and a modulus extractor, and a contrast detector furnishing, for each of these target ranges, said elementary raw plot consisting of one word of 2 m bits, the weighting performed by said weighting circuit being such that it limits the maximum number of cyclically contiguous lines for which a single-speed target is detected to 2 m /4+1, said plot summarizer comprising: four read-only memories respectively addressed by a first, a second, a third and a fourth group of bits of said elementary raw plot and providing at their outputs corresponding digital signals of m+3 bits called pseudosummaries, said first group consisting of bits 0 to 2 m-1 -1 of the elementary raw plot, said second group consisting of bits 2 m-2 to 2 m-1 + 2 m-2 -1 of the elementary raw plot, said third group, complementary to said first group, consisting of bits 2 m-1 to 2 m -1 of the elementary raw plot and said fourth group, complementary to said second group, consisting of bits 2 m-1 +2 m-2 to 2 m -1 and 0 to 2 m-2 -1 of the elementary raw plot; and a logic circuit for reconstituting said elementary summary plot from said pseudosummaries provided by said four read-only memories.
Claim 3
Dependent Claim 239 words
A plot summarizer according to claim 1, wherein each of said pseudosummaries includes a target detection bit, a single-speed target bit and an m+1 bit word giving an estimated spectrum, and wherein said logic circuit comprises: four multiple-input AND gates, each connected to a separate one of said four memories, each of said multiple-input AND gates having a control input and a plurality of inputs receiving an m+1 bit word and a single-speed target bit from the memory to which it is connected; four two-input AND gates, one for each of said four memories, each two-input AND gate having an output connected to the control input of one of said multiple-input AND gates, an uncomplemented input receiving the single-speed target bit from a memory to which the multiple-input AND gate is connected and a complemented input receiving the target detection bit from the memory addressed by the group of bits complementary to the group addressing the memory to which the multiple-input AND gate is connected; a multiple OR gate having four multiple inputs respectively connected to the outputs of said four multiple AND gates, said OR gate supplying said bit V and said word containing information on the speed of the target of said elementary summary plot; and an OR gate having four inputs receiving respectively the target detection bits from said four read-only memories, said OR gate supplying said target detection bit D of said elementary summary plot.
Claim 4
Dependent Claim 68 words
A plot summarizer according to claim 1, wherein each of said pseudosummaries includes a target detection bit, a single-speed target bit and an m+1 bit word giving an estimated spectrum and wherein said pseudosummaries are supplied by said read-only memories under the control of addresses formed respectively by said first, second, third and fourth group of bits with zeros added in order to make up elementary raw plots.

References Cited (Backward Citations)

US4330781A Cited
US4389648A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-11-25 1989-05-27 1989-11-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-11-25 1993-05-27 1993-11-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-11-25 1997-05-27 1997-11-26 $7700.00 Window Closed / Lapsed

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