Detection circuit for detecting synchronous and asynchronous states in a phase-locked loop circuit

Claim 2

A detection circuit for detecting synchronous and asynchronous states is a phase-locked loop (PLL) circuit, said PLL circuit including a voltage controlled oscillator for generating an oscillation signal, a phase comparator for comparing said oscillation signal to an input signal, said phase comparator providing an output which includes a first frequency component when said PLL circuit is in said synchronous state and a second frequency component when said PLL circuit is in an asynchronous state, and a loop filter connected between said phase comparator and said voltage controlled oscillator for providing a control signal applied to said voltage controlled oscillator, said detection circuit comprising: processing means for generating a processed signal from said phase comparator output by removing said first frequency component from said phase comparator output; and detection signal generating means responsive to said processed signal for generating a detection signal indicating the synchronous or asynchronous state of said PLL circuit.

Claim 3

A detection circuit as claimed in claim 1, wherein said PLL circuit is part of a reproduction signal time axis error correcting device and said input signal is a particular frequency component contained in said reproduction signal.

Claim 4

A detection circuit as claimed in claim 1, wherein said detection signal generating means comprises: integrating means for integrating said processed signal to provide an integration signal; level decision means for generating said detection signal in accordance with the level of said integration signal.

Claim 5

A detection signal circuit as claimed in claim 1, wherein said detection signal generating means comprises: rectifying means for receiving and rectifying said processed signal; integrating means for receiving and integrating the output of said rectifying means to provide an integration signal; and level decision means for generating said detection signal in accordance with the level of said integration signal.

Claim 6

A detection circuit as claimed in claim 4, wherein said level decision means generates as said detection signal an asynchronous indication signal representing an asynchronous state of said PLL circuit when said integration signal exceeds a first predetermined value.

Claim 7

A detection circuit as claimed in claim 5, wherein said level decision means terminates said asynchronous indication signal when said integration signal falls below a second predetermined level lower than said first predetermined level.

Claim 8

A detection circuit as claimed in claim 1, wherein said processing means comprises a bandpass filter having a lower cut-off frequency higher than said first frequency.

Claim 9

A detection circuit as claimed in claim 1, wherein said detection signal generated by said level decision means varies a time constant of said loop filter.

Claim 10

A detection circuit as claimed in claim 1, wherein said PLL circuit is a part of a reproduction signal time axis error correcting device for a disk-type player, said first frequency component comprising at least a part of said reproduction signal which results from the eccentricity of the disk.

Claim 11

A detection circuit for detecting synchronous and asynchronous states in a phase-locked loop (PLL) circuit contained in a time axis error correcting device; said PLL circuit including a voltage controlled oscillator for generating an oscillation signal, a phase comparator providing an output which includes a first frequency component corresponding to a rotation frequency of said video disc when said PLL circuit is in said synchronous state and a second frequency component when said PLL circuit is in an asynchronous state, and a loop filter connected between said phase comparator and said voltage controlled oscillator for providing a control signal being applied to said voltage controlled oscillator; said detection circuit comprising: a bandpass filter for extracting said second frequency component from said output signal of said phase comparator; rectifying means for rectifying said second frequency component provided by said bandpass filter to provide a rectified signal; integration means for integrating said rectified signal and providing an integration signal; and level decision means for generating a detection signal indicating the synchronous or asynchronous state of said PLL circuit by comparing said integration signal with a predetermined level.

Claim 12

A detection circuit for detecting synchronous and asynchronous states in a phase-locked loop (PLL) circuit contained in a time axis error correcting device; said PLL circuit including a voltage controlled oscillator for generating an oscillation signal, a phase comparator providing an output which includes a first frequency component corresponding to a rotation frequency of said video disc when said PLL circuit is in said synchronous state and a second frequency component when said PLL circuit is in an asynchronous state, and a loop filter connected between said phase comparator and said voltage controlled oscillator for providing a control signal being applied to said voltage controlled oscillator; said detection circuit comprising: a bandpass filter for extracting said second frequency component from said output signal of said phase comparator; rectifying means for rectifying said second frequency component provided by said bandpass filter to provide a rectified signal; integration means for integrating said rectified signal and providing an integration signal; and level decision means for generating a detection signal indicating the synchronous or asynchronous state of said PLL circuit by comparing said integration signal with a predetermined level.

Claim 13

A detection circuit as claimed in claim 10, wherein said level decision means comprises a Schmitt trigger cicuit.

Claim 14

A detection circuit as claimed in claim 10, wherein said level decision means generates as said detection signal an asynchronous indication signal representing an asynchronous state of said PLL circuit when said integration signal exceeds a first predetermined value.

Claim 15

A detection circuit as claimed in claim 12, wherein said level decision means terminates said asynchronous indication signal when said integration signal falls below a second predetermined level lower than said first predetermined level.

Claim 16

A detection circuit as claimed in claim 10, wherein said detection signal generated by said level decision means varies a time constant of said loop filter.