US4554671A
Expired / Lapsed
US
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Delta modulated communication system
Assignee: Fujifilm Holdings Corp
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Filing: 1983-11-04
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Granted: 1985-11-19
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Expires: 2003-11-04
Abstract
Abstract A logarithmic delta modulated transmission system, comprising a logarithmic A/D converter (12) for outputting binary signals (16, 18) indicative of the polarity and size of the difference between an analog signal to be transmitted and a reconstructed signal (44), selection circuitry (22, 38) for sampling the polarity signal at a clock rate (20) and the size signals at a subharmonic (26, 34) of the clock rate, and outputting digital signals to be transmitted, and a logarithmic delta demodulator (42) for providing the reconstructed signal from the transmitted signals. The sizes of the difference are set to be logarithmic.
Inventors
- 👤 Galen R. Collins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:42
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/06; H04B14/062
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
222 words
A digital communication system for an analog signal, comprising: a companded A/D converter (12) for comparing said analog signal against a reference signal, said companded converter comprising a flash converter including a plurality of comparators (70-96) each receiving said analog signal and a signal derived from said reference signal, said converter outputting a step-size signal indicating the magnitude of the difference between said analog signal and said reference signal and a delta signal indicating the sign of said difference, said step size being companded, with the smallest step size associated with the smallest difference; a clock outputting a clock signal (20) at a clock rate; delta data selection means (22) receiving said clock signal and said delta signal for outputting a digital transmitted delta signal at a clock rate; a step clock (26, 34) connected to said clock and outputting a step clock signal at a step clock rate that is a predetermined subharmonic of said clock rate; step data selection means (38) receiving said step-size signal for outputting a digital transmitted step-size signal at the step clock rate; a companded delta demodulator (42) receiving said transmitted delta signal and said transmitted step-size signal for outputting an analog transmitted amplitude signal determined by the present and past transmitted delta and step-size signals, said transmitted amplitude signal being used as said reference signal.
Claim 2
Dependent Claim
222 words
A digital communication system for an analog signal, comprising: a companded A/D converter (12) for comparing said analog signal against a reference signal, said companded converter comprising a flash converter including a plurality of comparators (70-96) each receiving said analog signal and a signal derived from said reference signal, said converter outputting a step-size signal indicating the magnitude of the difference between said analog signal and said reference signal and a delta signal indicating the sign of said difference, said step size being companded, with the smallest step size associated with the smallest difference; a clock outputting a clock signal (20) at a clock rate; delta data selection means (22) receiving said clock signal and said delta signal for outputting a digital transmitted delta signal at a clock rate; a step clock (26, 34) connected to said clock and outputting a step clock signal at a step clock rate that is a predetermined subharmonic of said clock rate; step data selection means (38) receiving said step-size signal for outputting a digital transmitted step-size signal at the step clock rate; a companded delta demodulator (42) receiving said transmitted delta signal and said transmitted step-size signal for outputting an analog transmitted amplitude signal determined by the present and past transmitted delta and step-size signals, said transmitted amplitude signal being used as said reference signal.
Claim 3
Dependent Claim
53 words
A digital communication system, as recited in claim 1, further comprising a multiplexer for multiplexing said transmitted delta signal and said transmitted step-size signal into a serial signal and a receiving station for receiving said serial signal comprising a demultiplexer of said serial signal and a delta companded demodulator connected to said demultiplexer.
Claim 4
Dependent Claim
18 words
A digital communication system, as recited in claim 1, wherein the companded step sizes are logarithmic step sizes.
Claim 5
Dependent Claim
27 words
A digital communication system, as recited in claim 1, further comprising a multiplexer (48) receiving said digital transmitted step size signal and outputting a serial step-size signal.
Claim 6
Dependent Claim
45 words
A digital communication system, as recited in claim 4, further comprising a synchronizing circuit (26), controlled by said clock signal, for outputting a given sequence of digital signals and wherein said multiplexer receives said sequence for outputting it as part of said serial step-size signal.
Claim 7
Dependent Claim
35 words
A digital communication system, as recited in claim 1, further comprising a receiving station (FIG. 4) receiving said transmitted delta signal and said transmitted step-size signal, said receiving station comprising a companded delta demodulator (42).
Claim 8
Dependent Claim
47 words
A digital communication system, as recited in claim 4, further comprising a receiving station receiving said transmitted delta signal and said serial step-size signal, said receiving station comprising a demultiplexer (140) for demultiplexing said serial step-size signal and a companded delta demodulator (42) connected to said demultiplexer.
Claim 9
Dependent Claim
69 words
A digital communication system, as recited in claim 5, further comprising a receiving station receiving said transmitted delta signal and said serial step size signal, said receiving station comprising: a local clock signal (142); a frame locking circuit (160) for synchronizing said serial step-size signal with said local clock signal; a demultiplexer (140) for demultiplexing said serial step-size signal; and a companded delta demodulator (42) connected to said demultiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |