US4554643A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically erasable programmable MNOS read only memory
Assignee: Texas Instruments Inc
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Filing: 1982-07-08
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Granted: 1985-11-19
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Expires: 2002-07-08
Abstract
Abstract An electrically programmable read only memory or EPROM is formed by an MNOS process compatible with N-channel silicon gate manufacturing methods. Row address lines and gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions formed beneath thin field oxide. Each storage cell is an MNOS transistor having an enhancement mode MOS transistor in series with it. The gates of the MNOS transistors are program address lines for programming and are formed by first level polycrystalline silicon. Each MNOS transistor in the array is programmed to be a logic "1" or "0" by proper voltages applied to row, output and program address lines to store charge at the oxide-nitride interface and thus change the threshold voltage for selected transistors. Then readout is provided using the MOS series transistors for access. A very dense array results.
Inventors
- 👤 Chang-Kiang Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:47
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H; H10; H10W; H10W20/00; H10W20/40; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49826; Y10T29/49908; Y10T29/49925; Y10T29/49927; Y10T29/49929; Y10T29/49933
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
143 words
A method of making a semiconductor device comprising the steps of: forming a plurality of insulated gate field effect transistor cells in a face of semiconductor body, each of the transistor cells having an MNOS transistor and an MOS transistor, including for each transistor forming a source-drain path and a gate, the transistor cells being formed in a regular pattern to provide a memory array with the source-drain paths of the MNOS transistor and the MOS transistor being connected in series in each cell in the array; applying address lines to said face and programming lines to said face intersecting each cell in the array for programming the array of memory cells by applying voltage to the gates of both transistors in selected cells and reading the array by applying voltage to the gate of only the MOS transistor in a selected cell.
Claim 2
Independent Claim
143 words
A method of making a semiconductor device comprising the steps of: forming a plurality of insulated gate field effect transistor cells in a face of semiconductor body, each of the transistor cells having an MNOS transistor and an MOS transistor, including for each transistor forming a source-drain path and a gate, the transistor cells being formed in a regular pattern to provide a memory array with the source-drain paths of the MNOS transistor and the MOS transistor being connected in series in each cell in the array; applying address lines to said face and programming lines to said face intersecting each cell in the array for programming the array of memory cells by applying voltage to the gates of both transistors in selected cells and reading the array by applying voltage to the gate of only the MOS transistor in a selected cell.
Claim 3
Dependent Claim
38 words
A method according to claim 1 including the step of forming the source-drain paths of the MNOS transistor and MOS transistor in each cell between heavily-doped semiconductor regions which define the ground and output lines for the array.
Claim 4
Dependent Claim
19 words
A method according to claim 2 including the step of forming said ground and output lines beneath field oxide.
Claim 5
Dependent Claim
33 words
A method according to claim 2 including the steps of forming the gate of the MNOS transistor of first level polysilicon and forming the gate of the MOS transistor of second level polysilicon.
Claim 6
Dependent Claim
38 words
A method according to claim 2 including the steps of forming the gates of the MNOS transistors as parts of a column address lines and forming the gates of the MOS transistors as parts of row address lines.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |