US4554598A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single revolution disk sector formatter
Assignee: Bull HN Information Systems Inc
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Filing: 1984-05-25
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Granted: 1985-11-19
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Expires: 2004-05-25
Abstract
Abstract A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM and RAM. Control codes are read into a control first in-first out memory and data codes are read into a data first in-first out memory. The control codes are applied to a decoder whose output signals control cyclic redundancy check and error detection and correction logic as well as the data first in-first out memory. The serial output from both the data first in-first out memory and the cyclic redundancy check logic are written on disk track.
Inventors
- 👤 Bruce H. Tarbox
- 👤 Donald J. Rathbun
- 👤 Taian Su
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:04
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/0604; G06F3/0607; G06F3/0628; G06F3/0638; G06F3/064; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0674; G06F3/0676; G11; G11B; G11B20/00; G11B20/10; G11B20/12; G11B20/1217; G11B20/1252; G11B2220/00; G11B2220/20; G11B2220/25; G11B2220/2508
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
292 words
Apparatus for writing a predetermined format on a track of a mass storage disk drive during one revolution of the disk, said apparatus comprising: DMA controller means for storing a plurality of address signals and generating a sequence of said plurality of address signals; read only memory (ROM) means coupled to said DMA controller means and responsive to said sequence of said plurality of address signals for generating sequence of ROM signals representative of fixed data codes or control codes stored in first locations specified by said sequence of said plurality of address signals; decoder means coupled to said ROM means and responsive to said sequence of ROM signals representative of said control codes for generating a sequence of control signals; random access memory (RAM) means coupled to said ROM means and said decoder means and responsive to said sequence of said plurality of address signals for generating a sequence of RAM signals representative of variable data codes stored in second locations specified by selected ones of said sequence of said plurality of address signals; data first in-first out (FIFO) means coupled to said DMA controller means, said decoder means, said ROM means and said RAM means and responsive to a memory write signal, a first control signal in a first state and said sequence of RAM signals for storing a sequence of variable data codes, and responsive to said memory write signal, said first control signal in a second state, a second control signal and said sequence of ROM signals for storing a sequence of fixed data codes, said FIFO means generating an output signal serializing said sequence of fixed and said variable data codes in said predetermined format for writing on said track during said one revolution of the disk.
Claim 2
Dependent Claim
292 words
Apparatus for writing a predetermined format on a track of a mass storage disk drive during one revolution of the disk, said apparatus comprising: DMA controller means for storing a plurality of address signals and generating a sequence of said plurality of address signals; read only memory (ROM) means coupled to said DMA controller means and responsive to said sequence of said plurality of address signals for generating sequence of ROM signals representative of fixed data codes or control codes stored in first locations specified by said sequence of said plurality of address signals; decoder means coupled to said ROM means and responsive to said sequence of ROM signals representative of said control codes for generating a sequence of control signals; random access memory (RAM) means coupled to said ROM means and said decoder means and responsive to said sequence of said plurality of address signals for generating a sequence of RAM signals representative of variable data codes stored in second locations specified by selected ones of said sequence of said plurality of address signals; data first in-first out (FIFO) means coupled to said DMA controller means, said decoder means, said ROM means and said RAM means and responsive to a memory write signal, a first control signal in a first state and said sequence of RAM signals for storing a sequence of variable data codes, and responsive to said memory write signal, said first control signal in a second state, a second control signal and said sequence of ROM signals for storing a sequence of fixed data codes, said FIFO means generating an output signal serializing said sequence of fixed and said variable data codes in said predetermined format for writing on said track during said one revolution of the disk.
Claim 3
Dependent Claim
53 words
The apparatus of claim 1 further comprising: control FIFO means coupled to said decoder means for storing said sequence of control signals representative of a second control signal, a third control signal and a fourth control signal, and generating said first, second and third output control signals in conformance with said predetermined format.
Claim 4
Dependent Claim
91 words
The apparatus of claim 2 further comprising: cyclic redundancy check (CRC) means for verifying address field data coupled to said data FIFO and said control FIFO and responsive to said third output control signal for resetting said CRC means, and responsive to said output signal for calculating a first CRC character and a second CRC character, and responsive to said first output control signal for storing said first and said second CRC characters in said data FIFO means for transfer by said output signal to said track in said predetermined format.
Claim 5
Dependent Claim
110 words
The apparatus of claim 3 further comprising: error detection and correction (EDAC) means for verifying data field data coupled to said control FIFO means and said RAM means and responsive to said first output control signal for resetting said EDAC means, and responsive to said sequence of RAM signals representative of said data field data for generating a first, a second, a third and a fourth EDAC character, said EDAC means being responsive to said second output control signal for transferring said first, said second, said third and said fourth EDAC characters to said data FIFO means for transfer by said output signal to said track in said predetermined format.
References Cited (Backward Citations)
US4494156A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |