US4554540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal format detection circuit for digital radio paging receiver
Assignee: NEC Corp
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Filing: 1982-11-19
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Granted: 1985-11-19
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Expires: 2002-11-19
Abstract
Abstract A signal detection circuit for a digital radio paging receiver is provided for successfully detecting a desired signal. A demodulated carrier wave, modulated with a code having n bits, is written into an n-stage shift register in response to a clock pulse of frequency f s . The output stages of the shift register are scanned in response to a scan signal of frequency nf s in order to provide an output. The output is dependent on the coincidence of the shift register outputs with a predetermined code and is used to enable an address detector circuit which compares a received signal to the desired signal stored in a PROM.
Inventors
- 👤 Toshihiro Mori
- 👤 Koichi Nagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:58
CPC Classifications
H; H04; H04W; H04W88/00; H04W88/02; H04W88/022; H04W88/025; H04W88/026; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
174 words
A signal detection circuit for a digital radio paging receiver, including means for receiving and demodulating a carrier wave modulated with a calling signal which includes a synchronization codeword having n bits, n being an integer not less than 2; register means having m stages for storing the demodulated output in response to clock pulses having a frequency f s , m being an integer not less than 2; means for generating said clock pulses; combination circuit means, including at least one inverter circuit and at least one direct connection which are respectively coupled to the outputs of said register means such that outputs of said combination circuit means become a predetermined logical level when said register means stores said synchronization codeword; scanning means for sequentially scanning said outputs of said combination circuit means in response to a scan signal of a frequency kf s , k being equal to or greater than n; and means for determining whether said synchronization code word has been received, in response to output of said scanning means.
Claim 2
Dependent Claim
174 words
A signal detection circuit for a digital radio paging receiver, including means for receiving and demodulating a carrier wave modulated with a calling signal which includes a synchronization codeword having n bits, n being an integer not less than 2; register means having m stages for storing the demodulated output in response to clock pulses having a frequency f s , m being an integer not less than 2; means for generating said clock pulses; combination circuit means, including at least one inverter circuit and at least one direct connection which are respectively coupled to the outputs of said register means such that outputs of said combination circuit means become a predetermined logical level when said register means stores said synchronization codeword; scanning means for sequentially scanning said outputs of said combination circuit means in response to a scan signal of a frequency kf s , k being equal to or greater than n; and means for determining whether said synchronization code word has been received, in response to output of said scanning means.
Claim 3
Dependent Claim
70 words
A signal detection circuit as claimed in claim 1, wherein said scanning means includes a circuit for generating said scan signal in response to said clock pulses; m AND gates supplied with respective outputs of said combination circuit means and with said scan signal; and an OR gate supplied with outputs from said m AND gates, whereby the output of said OR gate provides the output of said scanning means.
Claim 4
Dependent Claim
50 words
A signal detection circuit as claimed in claim 2, in which the determining means comprises a counter for counting the outputs of said OR gate to produce a determination signal at a predetermined count; and gate means for reading out the counter output as an output of said determining means.
Claim 5
Dependent Claim
105 words
A signal detection circuit as claimed in claim 1, in which said calling signal further includes a preamble code signal and address codewords, and said signal detection circuit further comprises battery saving means; means for temporarily ceasing the operation of said battery saving means upon detection of said preamble signal out of said demodulated output; means responsive to the output of said determining means for continuously suspending the operation of said battery saving means; means for detecting out of said demodulated output the address code word assigned to said receiver; and means responsive to the output of said detecting means, for generating an alert signal.
Claim 6
Dependent Claim
163 words
A signal detection circuit including means for receiving and demodulating a carrier wave modulated with at least a code having n bits, n being an integer not less than 2; register means having m stages for storing the demodulated output in response to clock pulses having a frequency f s , m being an integer not less than 2; means for generating said clock pulses; combination circuit means, including at least one inverter circuit and at least one direct connection which are respectively coupled to the outputs of said register means so that outputs of said combination circuit means become a predetermined logical level when said register means stores a predetermined code; scanning means for sequentially scanning said outputs of said combination circuit means in response to a scan signal of a frequency kf s , k being equal to or greater than n; and means for determining whether said predetermined code has been detected, in response to output of said scanning means.
Claim 7
Dependent Claim
163 words
A signal detection circuit including means for receiving and demodulating a carrier wave modulated with at least a code having n bits, n being an integer not less than 2; register means having m stages for storing the demodulated output in response to clock pulses having a frequency f s , m being an integer not less than 2; means for generating said clock pulses; combination circuit means, including at least one inverter circuit and at least one direct connection which are respectively coupled to the outputs of said register means so that outputs of said combination circuit means become a predetermined logical level when said register means stores a predetermined code; scanning means for sequentially scanning said outputs of said combination circuit means in response to a scan signal of a frequency kf s , k being equal to or greater than n; and means for determining whether said predetermined code has been detected, in response to output of said scanning means.
Claim 8
Dependent Claim
71 words
A signal detection circuit as claimed in claim 5, wherein said scanning means comprises a circuit for generating said scan signal in response to said clock pulses, m AND gates supplied with the respective outputs of said combined circuit means and with said scan signal, and an OR gate supplied with outputs of said m AND gates, whereby the output of said OR gate provides the output of said scanning means.
Claim 9
Dependent Claim
50 words
A signal detection circuit as claimed in claim 6, in which the determining means comprises a counter for counting the outputs of said OR gate to produce a determination signal at a predetermined count; and gate means for reading out the counter output as an output of said determining means.
Claim 10
Dependent Claim
18 words
a signal detection circuit as claimed in claim 5, wherein both m and k are equal to n.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |