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US4554485A Expired / Lapsed US ⏱️ 0.0 years remaining

Solid-state image display device

Assignee: Panasonic Holdings Corp
•
Filing: 1983-05-17
•
Granted: 1985-11-19
•
Expires: 2003-05-17
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Abstract

Abstract A solid-stage image display device is disclosed in which an electron injection region of high impurity density is formed on a surface of a semiconductor substrate of low impurity density, while a phosphor region of electron excitation type is formed on the other surface of the semiconductor substrate. Light is emitted from the phosphor region by the electrons running non-scattered i.e., the running distance of the carriers is shorter than the mean free path thereof within the substrate along the thickness thereof. The amount of electrons required for luminescence and injected into the substrate is controlled and the light-emitting position is selected by a drive control region provided in the semiconductor substrate between the electron injection region and the phosphor region. The drive control region provides a potential barrier against the electrons to the potential distribution in the substrate, wtih the height of the potential barrier being controlled by the voltage applied to the drive control region.

Inventors

  • 👤 Takahiro Yamada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 23:57
CPC Classifications
H; H10; H10H; H10H20/00; H10H29/00; H10H29/10; H10H29/14; H10H29/142

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 142 words
A solid-state image display device comprising: a phosphor region acting as a drain region and formed on a surface of a semiconductor substrate having a low impurity density, a carrier supply region of a first conduction type, having a high impurity density and formed on another surface of said semi-conductor substrate, opposite to said surface having said phosphor region formed thereon, and a gate region of a second conduction type formed on said another surface of said semiconductor substrate, for controlling an amount of carriers injected from said carrier supply region into said semiconductor substrate, wherein said carriers injected from said carrier supply region into said semiconductor substrate reach said phosphor region by running in a non-scattered manner such that a running distance of said carriers is shorter than a mean free path thereof, thereby causing light emission from said phosphor region.
Claim 2
Dependent Claim 142 words
A solid-state image display device comprising: a phosphor region acting as a drain region and formed on a surface of a semiconductor substrate having a low impurity density, a carrier supply region of a first conduction type, having a high impurity density and formed on another surface of said semi-conductor substrate, opposite to said surface having said phosphor region formed thereon, and a gate region of a second conduction type formed on said another surface of said semiconductor substrate, for controlling an amount of carriers injected from said carrier supply region into said semiconductor substrate, wherein said carriers injected from said carrier supply region into said semiconductor substrate reach said phosphor region by running in a non-scattered manner such that a running distance of said carriers is shorter than a mean free path thereof, thereby causing light emission from said phosphor region.
Claim 3
Dependent Claim 31 words
A solid-state image display device according to claim 1, wherein a potential of said gate region is controlled by a potential of a carrier storage region of said second conduction type.
Claim 4
Dependent Claim 26 words
A solid-state image display device according to claim 1, further comprising scanning means for selecting positions of a plurality of said gate regions arranged in matrix.
Claim 5
Dependent Claim 76 words
A solid-state image display device according to claim 1, wherein said gate region includes a pair of resistive gate regions formed continuously in one scanning direction, and further comprising means for applying DC voltages across respective said resistive gate regions in opposite directions such that potentials across said respective resistive gate regions have opposite polarities, and means for applying a pair of saw-tooth waves in inverted forms in AC fashion to said resistive gate regions respectively.

References Cited (Backward Citations)

US3564135A Cited
US3806759A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-11-18 1989-05-20 1989-11-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-11-18 1993-05-20 1993-11-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-11-18 1997-05-20 1997-11-19 $7700.00 Window Closed / Lapsed

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