Circuit and process for chrominance decoding with analog or digital delay line in a television system of a pal or secam type

Claim 2

A process for manufacturing a chrominance decoding circuit, comprising the following steps; using a conventional chrominance decoding circuit formed more especially from an integrated circuit whose two terminals are intended to be connected to a conventional analog delay line and whose two output terminals are intended to supply the chrominance signals B-Y and R-Y, not connecting the analog delay line, connecting the outputs of the circuit to a digital-delay line matching circuit comprising: a first channel connecting the first output terminal to a first input of a first summator, a second channel connecting the second output terminal to a first input of a second summator, a third channel comprising successively: a switch with two inputs and one output in which each input is connected alternately to each of the outputs of the integrated circuit, at a frequency H1, an analog-digital convertor actuated at a frequency H2, a digital delay line actuated at the frequency H2, a digital-analog convertor, a switch with one input and two outputs, each output being connected to a second input of the first and second summators at frequency H1, the outputs of the summators supplying signals B-Y and R-Y.

Claim 3

A chrominance decoding circuit with digital delay line for a system of the PAL or SECAM type comprising a conventional chrominance decoding circuit itself comprising an integrated circuit having two terminals normally connected to a conventional analog delay line, for example a volume wave line, and two output terminals normally supplying, when the conventional delay line is connected, the chrominance signals R-Y and B-Y, wherein the delay line is not used and the corresponding terminals are not connected, this decoding circuit further comprising a matching circuit connected to the output terminals of the conventional circuit, this matching circuit comprising: a first channel connecting the first output terminal to a first input of a first summator, a second channel connecting the second output terminal to a first input of a second summator, a third channel comprising successively: a switch with two inputs and one output in which each input is connected alternately to each of the outputs of the conventional circuit, at a frequency H1, an analog-digital convertor actuated at a frequency H2, a digital delay line actuated at frequency H2, a digital-analog convertor, a switch with one input and two outputs, each output being connected to a second input of the first and second summators, at frequency H1, the outputs of the summator supplying the signals B-Y and R-Y.

Claim 4

A chrominance decoding circuit with digital delay line for a system of the PAL or SECAM type comprising a conventional chrominance decoding circuit itself comprising an integrated circuit having two terminals normally connected to a conventional analog delay line, for example a volume wave line, and two output terminals normally supplying, when the conventional delay line is connected, the chrominance signals R-Y and B-Y, wherein the delay line is not used and the corresponding terminals are not connected, this decoding circuit further comprising a matching circuit connected to the output terminals of the conventional circuit, this matching circuit comprising: a first channel connecting the first output terminal to a first input of a first summator, a second channel connecting the second output terminal to a first input of a second summator, a third channel comprising successively: a switch with two inputs and one output in which each input is connected alternately to each of the outputs of the conventional circuit, at a frequency H1, an analog-digital convertor actuated at a frequency H2, a digital delay line actuated at frequency H2, a digital-analog convertor, a switch with one input and two outputs, each output being connected to a second input of the first and second summators, at frequency H1, the outputs of the summator supplying the signals B-Y and R-Y.

Claim 5

The chrominance decoding circuit as claimed in claim 2, wherein said digital delay line is a shift register with n parallel bits and with a number of cells p such that p/H2 is equal to the desired delay.

Claim 6

The chrominance decoding circuit as claimed in claim 2, adapted to the PAL system, wherein said frequency H2 is the frequency of the color sub-carrier and the frequency H1 is equal to half this frequency.

Claim 7

The chrominance decoding circuit as claimed in claim 2, adapted to the SECAM system, wherein said frequency H2 is a frequency close to the color sub-carrier frequencies and the frequency H1 is equal to the line half frequency.