US4551704A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Look-back analog to digital converter
Assignee: International Business Machines Corp
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Filing: 1983-09-27
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Granted: 1985-11-05
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Expires: 2003-09-27
Abstract
Abstract In an analog-to-digital converter implemented in logic operating on the multiple lobes of a threshold curve, such as Josephson SQUIDs, two sampling registers are provided with sufficient offset to guarantee stability at sampling in one or the other regardless of other factors. Knowledge of bit value of the next lower bit order position permits determination of which sampling is valid. Encoder logic selects the valid sampling register retroactively. Each sampling register bit order position has two sampling SQUIDs and latching self-gated ANDs. Bias values are provided at higher orders to increment the phase offset so as to ensure low-to-high order readout. The lowest two bit orders may be implemented in simplified logic, effectively giving two bit order positions for logic and SQUIDs equal to that of one higher order bit position.
Inventors
- 👤 Carl J. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
230 words
An ordered register subsystem, for a high speed data processing system, having interconnected analog input means, register/encoder means and output utilization means characterized by (a) base sampling register means, having ordered bit positions settable to analog threshold values in response to an analog input signal, connected to the analog input means, forming part of the register/encoder means; (b) offset sampling register means, having ordered bit positions settable to analog threshold values in response to an analog input signal, connected to the analog input means, forming part of the register/encoder means; (c) base sampling interval phasing means connected to said base sampling register means in sampling control configuration; (d) offset sampling interval phasing means, offset in phase from said base sampling interval phasing means, connected to said offset sampling register means in sampling control configuration; (e) sample encoding means, connected to said base and offset sampling register means, responsive to threshold value settings of said base and offset sampling register means, and to its own output signals from respectively lower bit order positions, to encode in sequence, on a bit order position basis, as a function of respective next lower order bit position bit values, the respective composite values of respective next lower order bit position and of said base sampling register means, or alternatively the composite values of respective next lower order bit position and of offset sampling register means.
Claim 2
Dependent Claim
230 words
An ordered register subsystem, for a high speed data processing system, having interconnected analog input means, register/encoder means and output utilization means characterized by (a) base sampling register means, having ordered bit positions settable to analog threshold values in response to an analog input signal, connected to the analog input means, forming part of the register/encoder means; (b) offset sampling register means, having ordered bit positions settable to analog threshold values in response to an analog input signal, connected to the analog input means, forming part of the register/encoder means; (c) base sampling interval phasing means connected to said base sampling register means in sampling control configuration; (d) offset sampling interval phasing means, offset in phase from said base sampling interval phasing means, connected to said offset sampling register means in sampling control configuration; (e) sample encoding means, connected to said base and offset sampling register means, responsive to threshold value settings of said base and offset sampling register means, and to its own output signals from respectively lower bit order positions, to encode in sequence, on a bit order position basis, as a function of respective next lower order bit position bit values, the respective composite values of respective next lower order bit position and of said base sampling register means, or alternatively the composite values of respective next lower order bit position and of offset sampling register means.
Claim 3
Dependent Claim
25 words
An ordered register subsystem according to claim 1 further characterized in that the offset of said offset sample interval phasing means is approximately 90 degrees.
Claim 4
Dependent Claim
60 words
An ordered register subsystem according to claim 1 further characterized by said offset sample interval phasing means includes offset increment sample interval phasing means, offset from said base sampling interval phasing means by an increment over the offset of said offset sampling interval phasing means, to provide additional offset to adjust sampling interval phasing additionally for higher order bit positions.
Claim 5
Dependent Claim
43 words
An ordered register subsystem according to claim 3 further characterized in that said offset increment sample interval phasing means is phase shifted: -((2.sup.n-2 -1)/2.sup.n)180 where n is the bit order position and the phase of bit positions 1 and 2 is 0 degrees.
Claim 6
Dependent Claim
117 words
An ordered register subsystem according to claim 1 further characterized in that said sample encoding means includes for the base low order bit position a direct connection of said base sampling register means base low order position to the output utilization means; and said offset sampling register means includes an offset low order position, lower than said base low order bit position, and said sample encoding means includes means connecting said offset sampling register means via said sampling register encoding means to the utilization means, whereby the implementation complexity of the base low order bit position and of the offset extra low order position together approximates the implementation complexity of internal bit order positions of the subsystem.
Claim 7
Dependent Claim
58 words
An analog to digital converter according to claim 5 further characterized in that said base sampling register means and said offset sampling register means are implemented in latching superconductive Josephson technology, including self-gated AND circuits and SQUIDs, and said offset increment sampling interval phasing means is implemented as DC bias windings applying appropriate vias voltages to said SQUIDs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-04 | 1989-05-06 | 1989-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-04 | 1993-05-06 | 1993-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-04 | 1997-05-06 | 1997-11-05 | $7700.00 | Window Closed / Lapsed |