Address sequencer for pattern processing system

Claim 2

Apparatus for generating an address stream which includes a plurality of interleaved sequences of addresses, the apparatus comprising: means for providing a sequence identification number which identifies a selected sequence of the plurality of sequences; means for providing an address of the selected sequence in response to the sequence identification number; means for providing input data in response to the address of the selected sequence; shift register means for containing bits in a plurality of stages, the bits being initially based upon the address of the selected sequence; means for shifting the contents of the shift register means by a predetermined number of stages; means for deriving bits from selected stages of the shift register means as a function of the sequence identification number; means for feeding back a feedback bit into the shift register means, the feedback bit being a function of the bits derived from the selected stages; means for selecting a next address in the selected sequence as a function of the input data and the contents of the shift register means after the contents have been shifted by a predetermined number of stages; and means for storing the selected next address for use when the sequence identification number is again provided.

Claim 3

The apparatus of claim 1 wherein the means for selecting comprises: means for comparing the input data and a reference value and providing a first comparator output when the input data and the reference value have a first relationship and a second comparator output when the input data and the reference value have a second relationship; and select means for selecting a first arrangement of the contents of the shift register means as the next address in response to the first comparator output and a second arrangement of the contents of the shift register means as the next address in response to the second comparator output.

Claim 4

The apparatus of claim 2 wherein each sequence identification number has a reference value associated therewith, and wherein the means for providing a sequence identification number provides the reference value associated with the sequence identification number to the means for comparing.

Claim 5

The apparatus of claim 3 wherein the means for providing a sequence identification number is a counter which contains a count which is changed at commencement of each cycle of operation of the apparatus, and wherein the sequence identification number and the reference value are based upon the count.

Claim 6

The apparatus of claim 2 wherein the select means comprises: means for routing the first arrangement of the contents of the shift register means to the means for storing in response to the first comparator output; and means for routing the second arrangement of the contents of the shift register means to the means for storing in response to the second comparator output.

Claim 7

The apparatus of claim 1 and further comprising: means for loading a multibit word which is a function of the address of the selected sequence into the shift register means prior to shifting of the contents of the shift register means.

Claim 8

The apparatus of claim 6 wherein the means for loading comprises: means for routing a first arrangement of bits of the address to the shift register means as the multibit word if the input data and a reference value have a first relationship; and means for routing a second arrangement of bits of the address to the shift register means as the multibit word if the input data and the reference value have a second relationship.

Claim 9

The apparatus of claim 1 and further comprising: means for providing the address and the sequence identification number as an output of the apparatus, so that each address of the address stream has a sequence identification number associated therewith.

Claim 10

The apparatus of claim 1 wherein the means for storing comprises: first storage means for storing an initial address for each sequence identification number to be used during a first cycle of operation for each sequence; and second read/write storage means for storing the next address selected for each sequence identification number.

Claim 11

The apparatus of claim 1 wherein the means for deriving comprises: tap storage means for storing a digital word representative of the selected stages for each sequence identification number, the tap storage means being addressable by the sequence identification number; and means for routing bits from the selected stages to the means for feeding back based upon the digital word read from the tap storage means in response to the sequence identification number.

Claim 12

The apparatus of claim 10 wherein the means for feeding back comprises an exclusive-OR circuit for exclusive-ORing the bits from the selected taps to produce the feedback bit.

Claim 13

Apparatus for generating an address stream at an output which includes a plurality of interleaved sequences of addresses, the sequences of addresses being a function of input data received at an input in response to the address stream, the apparatus comprising: sequence identification means for providing a sequence identification number which identifies one of the plurality of sequences; storage means for storing an address for each sequence identification number; output means for providing an address to the output; shift register means for containing bits in a plurality of stages; load means for loading a multibit word into the shift register means; shift means for causing the shift register means to shift its contents by a predetermined number of stages; tap means for deriving bits from selected stages of the shift register means, the selected stages being a function of the sequence identification number; feedback means for providing a feedback bit of the shift register means during each shift of the contents by one stage, wherein the feedback bit is a function of the bits from the selected stages; select means for selecting a next address of the sequence based upon the input data received in response to the address provided to the output and the contents of the shift register means after the shift by the predetermined number of stages; and control means for controlling the apparatus to generate the address stream during a series of operating cycles wherein during each cycle the control means causes the sequence identification means to provide a new sequence identification number; causes the stored address corresponding to the new sequence identification number to be provided by the output means to the output; causes the load means to load into the shift register means a multibit word which is a function of the stored address corresponding to the new sequence identification number; enables the shift means; and causes the next address selected by the select means to be stored in the storage means at the address corresponding to the sequence identification number.

Claim 14

Apparatus for generating an address stream at an output which includes a plurality of interleaved sequences of addresses, the sequences of addresses being a function of input data received at an input in response to the address stream, the apparatus comprising: sequence identification means for providing a sequence identification number which identifies one of the plurality of sequences; storage means for storing an address for each sequence identification number; output means for providing an address to the output; shift register means for containing bits in a plurality of stages; load means for loading a multibit word into the shift register means; shift means for causing the shift register means to shift its contents by a predetermined number of stages; tap means for deriving bits from selected stages of the shift register means, the selected stages being a function of the sequence identification number; feedback means for providing a feedback bit of the shift register means during each shift of the contents by one stage, wherein the feedback bit is a function of the bits from the selected stages; select means for selecting a next address of the sequence based upon the input data received in response to the address provided to the output and the contents of the shift register means after the shift by the predetermined number of stages; and control means for controlling the apparatus to generate the address stream during a series of operating cycles wherein during each cycle the control means causes the sequence identification means to provide a new sequence identification number; causes the stored address corresponding to the new sequence identification number to be provided by the output means to the output; causes the load means to load into the shift register means a multibit word which is a function of the stored address corresponding to the new sequence identification number; enables the shift means; and causes the next address selected by the select means to be stored in the storage means at the address corresponding to the sequence identification number.

Claim 15

The apparatus of claim 12 wherein the select means comprises: comparator means for comparing the input data and a reference value and providing a first comparator output when the input data and the reference value have a first relationship and a second comparator output when the input data and the reference value have a second relationship; and means for selecting a first arrangement of the contents of the shift register means as the next address in response to the first comparator output and a second arrangement of the contents of the shift register means as the next address in response to the second comparator output.

Claim 16

The apparatus of claim 13 wherein each sequence identification number has a reference value associated therewith, and wherein during each cycle the sequence identification means provides to the comparator means the reference value associated with the sequence identification number in use during that cycle.

Claim 17

The apparatus of claim 14 wherein the sequence identification means is a counter which contains a count which is changed in response to the control means at commencement of each cycle, and wherein the sequence identification number and the reference value are based upon the count.

Claim 18

The apparatus of claim 13 wherein the means for selecting comprises: first transceiver means for routing the first arrangement of the contents of the shift register means to the storage means in response to the first comparator output and a first direction control signal from the control means; and second transceiver means for routing the second arrangement of the contents of the shift register means to the storage means in response to the second comparator output and the first direction control signal.

Claim 19

The apparatus of claim 16 wherein the load means comprises the first and second transceiver means, wherein the first transceiver means routes a first arrangement of the address from the storage means to the shift register means as the multibit word in response to the first comparator output and a second direction control signal from the control means, and wherein the second transceiver means routes a second arrangement of the address from the storage means to the shift register means as the multibit word in response to the second comparator output and the second direction control signal.

Claim 20

The apparatus of claim 12 wherein the output means also provides the sequence identification number to the output, so that each address of the address stream has a sequence identification number associated therewith.

Claim 21

The apparatus of claim 12 wherein the storage means comprises: first storage means for storing an initial address for each sequence identification number to be used during a first cycle for each sequence; and second read/write storage means for storing the next address selected by the select means for each sequence identification number.

Claim 22

The apparatus of claim 19 wherein the first storage means stores the initial addresses in locations which are addressable by their respective sequence identification numbers, and wherein the initial address stored in the location addressed by the sequence identification means is read out from the first storage means in response to a signal from the control means.

Claim 23

The apparatus of claim 19 wherein the second storage means stores the next addresses in locations which are addressable by their respective sequence identification numbers, and wherein the next address selected by the select means is written into the location addressed by the sequence identification means in response to a write enable signal from the control means.

Claim 24

The apparatus of claim 12 wherein the tap means comprises: tap storage means for storing a digital word representative of the selected stages for each sequence identification number, the tap storage means being addressable by the sequence identification number; and means for routing bits from the selected stages to the feedback means based upon the word read from the tap storage means in response to the sequence identification number.

Claim 25

The apparatus of claim 22 wherein the feedback means comprises an exclusive-OR circuit for exclusive-ORing the bits from the selected taps to produce the feedback bit.

Claim 26

Apparatus for generating a sequence of addresses, the apparatus comprising: means for providing a multibit address; means for providing input data in response to the multibit address; shift register means for containing bits in a plurality of stages, the bits being related to the multibit address; means for causing the shift register means to shift the bits by a predetermined number of stages; means for loading a feedback bit into the shift register means each time the bits are shifted by one stage, wherein the feedback bit is a function of bits from selected stages of the shift register means, so that the contents of the shift register means after the shift are a function of the contents prior to the shift; and means for selecting a next address in the sequence derived from the contents of the shift register means after the shift by a predetermined number of stages, wherein the means for selecting selects the next address from a plurality of possible next addresses which could be derived from the contents of the shift register means based upon a value of the input data.

Claim 27

Apparatus for generating a sequence of addresses, the apparatus comprising: means for providing a multibit address; means for providing input data in response to the multibit address; shift register means for containing bits in a plurality of stages, the bits being related to the multibit address; means for causing the shift register means to shift the bits by a predetermined number of stages; means for loading a feedback bit into the shift register means each time the bits are shifted by one stage, wherein the feedback bit is a function of bits from selected stages of the shift register means, so that the contents of the shift register means after the shift are a function of the contents prior to the shift; and means for selecting a next address in the sequence derived from the contents of the shift register means after the shift by a predetermined number of stages, wherein the means for selecting selects the next address from a plurality of possible next addresses which could be derived from the contents of the shift register means based upon a value of the input data.

Claim 28

The apparatus of claim 24 wherein the means for selecting comprises: comparator means for comparing the input data and a reference value and providing a first comparator output when the input value and the reference value have a first relationship and a second comparator output when the input value and the reference value have a second relationship; and means for selecting a first arrangement of the contents of the shift register means as the next address in response to the first comparator output and a second arrangement of the contents of the shift register means as the next address in response to the second comparator output.

Claim 29

A pattern processing system for identifying image input patterns, the system comprising: addressable means for providing multibit grey scale values representative of an image input pattern at a plurality of addressable locations; address sequencer means for providing an address stream which includes a plurality of interleaved sequences of addresses, wherein each next address of each sequence is determined by a present address of that sequence and the multibit grey scale value from the location corresponding to the present address of the sequence, the address sequencer means comprising: means for periodically providing a sequence identification number which identifies a selected sequence of the plurality; means for providing the present address of the selected sequence as part of the address stream based upon the sequence identification number; means for periodically providing a reference value representative of one of a plurality of possible grey scale levels; means for comparing the grey scale value with the reference value; means for providing a next address of the selected sequence as a function of the present address and the comparison of the multibit grey scale value and the reference value; and means for storing the next address for use as the present address when the sequence identification number is again provided; and means responsive to the address stream for identifying image input patterns based upon address loops contained in the address stream which were caused by the image input pattern.

Claim 30

A pattern processing system for identifying image input patterns, the system comprising: addressable means for providing multibit grey scale values representative of an image input pattern at a plurality of addressable locations; address sequencer means for providing an address stream which includes a plurality of interleaved sequences of addresses, wherein each next address of each sequence is determined by a present address of that sequence and the multibit grey scale value from the location corresponding to the present address of the sequence, the address sequencer means comprising: means for periodically providing a sequence identification number which identifies a selected sequence of the plurality; means for providing the present address of the selected sequence as part of the address stream based upon the sequence identification number; means for periodically providing a reference value representative of one of a plurality of possible grey scale levels; means for comparing the grey scale value with the reference value; means for providing a next address of the selected sequence as a function of the present address and the comparison of the multibit grey scale value and the reference value; and means for storing the next address for use as the present address when the sequence identification number is again provided; and means responsive to the address stream for identifying image input patterns based upon address loops contained in the address stream which were caused by the image input pattern.

Claim 31

The system of claim 26 wherein the means for providing a next address comprises: shift register means for containing bits in a plurality of stages, the bits being initially based upon the present address; means for shifting the contents of the shift register means by a predetermined number of stages; means for deriving bits from selected stages of the shift register means as a function of the sequence identification number; means for feeding back a feedback bit into the shift register means, the feedback bit being a function of the bits derived from the selected stages; and means for selecting a next address in the selected sequence as a function of the comparison and the contents of the shift register means after the contents have been shifted by a predetermined number of stages.

Claim 32

The system of claim 27 wherein the means for comparing the grey scale value and the reference value provides a first comparator output when the grey scale value and the reference value have a first relationship and a second comparator output when the grey scale value and the reference value have a second relationship; and wherein the means for selecting a next address selects a first arrangement of the contents of the shift register means as the next address in response to the first comparator output and a second arrangement of the contents of the shift register means as the next address in response to the second comparator output.

Claim 33

The system of claim 27 wherein each sequence identification number has a reference value associated therewith, and wherein the means for providing a sequence identification number provides reference value associated with the sequence identification number to the means for comparing.

Claim 34

The system of claim 27 and further comprising: means for loading a multibit word which is a function of the present address of the selected sequence into the shift register means prior to shifting of the contents of the shift register means.

Claim 35

The system of claim 30 wherein the means for loading comprises: means for routing a first arrangement of bits of the address to the shift register means as the multibit word if the grey scale value and the reference value have a first relationship; and means for routing a second arrangement of bits of the address to the shift register means as the multibit word if the grey scale value and the reference value have a second relationship.

Claim 36

The system of claim 27 wherein the means for deriving comprises: tap storage means for storing a digital word representative of the selected stages for each sequence identification number, the tap storage means being addressable by the sequence identification number; and means for routing bits from the selected stages to the means for feeding back based upon the digital word read from the tap storage means in response to the sequence identification number.

Claim 37

The system of claim 32 wherein the means for feeding back comprises an exclusive-OR circuit for exclusive-ORing the bits from the selected taps to produce the feedback bit.

Claim 38

The system of claim 26 wherein the means for storing comprises: first storage means for storing an initial address for each sequence identification number to be used as the present address during a first cycle of operation for each sequence; and second read/write storage means for storing the next address produced for each sequence identification number.

Claim 39

The system of claim 26 and further comprising: means for providing with each present address the sequence identification number which identifies the sequence of which the present address is a part so that each address of the address stream has a sequence identification number associated therewith.