Control circuit for switching inductive loads

Claim 2

A control circuit for switching an inductive load, said circuit comprising: a control circuit means connected to a source of switching signals, said means generating electrical pulses in response to said signals, said pulses each having a leading and trailing edge; a first and a second transistor, each having a first, a second, and a control terminal; wherein one of said first and second terminals of said first transistor is connected to one terminal of a two terminal D.C. supply voltage, the other of said first and second terminals and said control terminal of said first transistor being respectively connected to said control terminal of said second transistor and to said control circuit means, said first transistor being made conductive by said pulses generated by said circuit means; wherein the second transistor, by means of its first and second terminals, is inserted in series with an inductive load which is connected between said two terminals of said D.C. supply voltage; further comprising a charge removing circuit means, connected to the control terminal of at least one of said first and second transistors for removing a charge therefrom and coupled to the control circuit means which controls the activation thereof in correspondance with said trailing edge of each of said pulses which make said first transistor conductive, and still further comprising a timed enabling circuit means which is also coupled to said control circuit means which is enabled by said enabling circuit means so as to keep said charge removing circuit means operative for a fixed period of time, which is at most equal to the period of time which elapses between said trailing edge of each of said pulses and said leading edge of the following one of said pulses.

Claim 3

A circuit according to claim 1, wherein said first and second transistors are respectively of a first and a second type of conductivity which are opposite to one another, and wherein said first and second terminals of said first transistor are respectively connected to a first terminal of said D.C. supply voltage and to said control terminal of said second transistor, and wherein said first and second terminals of said second transistor are respectively connected to a second terminal of said D.C. supply voltage through said inductive load and to said first terminal of said D.C. supply voltage.

Claim 4

A control circuit for switching an inductive load, said circuit comprising: a control circuit means connected to a source of switching signals, said means generating electrical pulses in response to said signals, said pulses each having a leading and trailing edge; a first and a second transistor, each having a first, a second, and a control terminal; wherein one of said first and second terminals of said first transistor is connected to one terminal of a two terminal D.C. supply voltage, the other of said first and second terminals and said control terminal of said first transistor being respectively connected to said control terminal of said second transistor and to said control circuit means, said first transistor being made conductive by said pulses generated by said circuit means; wherein the second transistor, by means of its first and second terminals, is inserted in series with an inductive load connected between said two terminals of said D.C. supply voltage; further comprising a charge removing circuit means, connected to the control terminal of at least one of said first and second transistors for removing a charge therefrom and coupled to the control circuit means which controls the activation thereof in correspondance with said trailing edge of each of said pulses which make said first transistor conductive, and still further comprising a timed enabling circuit means which is also coupled to said control circuit means which is enabled to said enabling circuit means so as to keep said charge removing circuit means operative for a fixed period of time, which is at most equal to the period of time which elapses between said trailing edge of each of said pulses and said leading edge of the following one of said pulses; wherein said first and second transistors are respectively of a first and a second type of conductivity which are opposite to one another, and wherein said first and second terminals of said first transistor are respectively connected to a first terminal of said D.C. supply voltage and to said control terminal of said second transistor, and wherein said first and second terminals of said second transistor are respectively connected to a second terminal of said D.C. supply voltage through said inductive load and to said first terminal of said D.C. supply voltage; wherein said charge removing circuit means comprises a third, a fourth, and a fifth transistor, each transistor having a first, a second, and a control terminal, said third and fourth transistor being of said first type of conductivity and said fifth transistor being of said second type of conductivity, wherein said control terminals of said third and fourth transistors are both connected to a cathode of a first diode and to said control circuit means, and an anode of said first diode and said first terminal of said third and fourth transistors are connected to said first terminal of said D.C. supply voltage, and wherein said second terminal of said third transistor is connected to said control terminal of said first transistor, and said second terminal of said fourth transistor is connected to said control terminal of said fifth transistor, and said first terminal of said fifth transistor is connected to both its own control terminal through a first resistive element and to said first terminal of said second transistor, and said second terminal of said fifth transistor is connected to said control terminal of said second transistor.

Claim 5

A control circuit for switching an inductive load, said circuit comprising: a control circuit means connected to a source of switching signals, said means generating electrical pulses in response to said signals, said pulses each having a leading and trailing edge; a first and a second transistor, each having a first, a second, and a control terminal; wherein one of said first and second terminals of said first transistor is connected to one terminal of a two terminal D.C. supply voltage, the other of said first and second terminals and said control terminal of said first transistor being respectively connected to said control terminal of said second transistor and to said control circuit means, said first transistor being made conductive by said pulses generated by said circuit means; wherein the second transistor, by means of its first and second terminals, is inserted in series with an inductive load connected between said two terminals of said D.C. supply voltage; further comprising a charge removing circuit means, connected to the control terminal of at least one of said first and second transistors for removing a charge therefrom and coupled to the control circuit means which controls the activation thereof in correspondance with said trailing edge of each of said pulses which make said first transistor conductive, and still further comprising a timed enabling circuit means which is also coupled to said control circuit means which is enabled to said enabling circuit means so as to keep said charge removing circuit means operative for a fixed period of time, which is at most equal to the period of time which elapses between said trailing edge of each of said pulses and said leading edge of the following one of said pulses; wherein said first and second transistors are respectively of a first and a second type of conductivity which are opposite to one another, and wherein said first and second terminals of said first transistor are respectively connected to a first terminal of said D.C. supply voltage and to said control terminal of said second transistor, and wherein said first and second terminals of said second transistor are respectively connected to a second terminal of said D.C. supply voltage through said inductive load and to said first terminal of said D.C. supply voltage; wherein said charge removing circuit means comprises a third, a fourth, and a fifth transistor, each transistor having a first, a second, and a control terminal, said third and fourth transistor being of said first type of conductivity and said fifth transistor being of said second type of conductivity, wherein said control terminals of said third and fourth transistors are both connected to a cathode of a first diode and to said control circuit means, and an anode of said first diode and said first terminal of said third and fourth transistors are connected to said first terminal of said D.C. supply voltage, and wherein said second terminal of said third transistor is connected to said control terminal of said first transistor, and said second terminal of said fourth transistor is connected to said control terminal of said fifth transistor, and said first terminal of said fifth transistor is connected to both its own control terminal through a first resistive element and to said first terminal of said second transistor, and said second terminal of said fifth transistor is connected to said control terminal of said second transistor.

Claim 6

A circuit according to claim 3, wherein said charge removing circuit means comprises a sixth and a seventh transistor, said sixth and seventh transistors respectively being of said first and second types of conductivity and each having a first, a second and a control terminal, wherein said control terminal of said sixth transistor is connected to said cathode of said first diode and to said control circuit means, and said first and second terminals of said sixth transistor are respectively connected to said first terminal of said DC supply voltage and to said control terminal of said seventh transistor, and wherein said first and second terminals of said seventh transistor are respectively connected to said second terminal of said D.C. supply voltage, to which is also connected said control terminal of said seventh transistor through a second resistive element, and a cathode of a second diode, an anode of which is connected to said control terminal of said second transistor.

Claim 7

A circuit according to claim 3, wherein said resistive element comprises a resistor.

Claim 8

A circuit according to claim 3, wherein said resistive element comprises a diode.

Claim 9

A circuit according to claim 4, wherein said resistive elements comprise resistors.

Claim 10

A circuit according to claim 4, wherein said resistive elements comprise diodes.

Claim 11

A circuit according to claim 3, wherein said control circuit means comprises eighth, ninth and tenth transistors, said eighth, ninth, and tenth transistors being of said second type of conductivity and each having first, second, and control terminals, wherein: said control terminals of said eighth and ninth transistor are connected to said source of switching signals, and to an anode of a third diode, a cathode of said third diode being connected to said second terminal of said D.C. supply voltage; said first and second terminals of said eighth transistor are respectively connected to said second terminal of said D.C. supply voltage and to both said control terminal of said first transistor and to a cathode of a fourth diode, an anode of said fourth diode being connected to said first terminal of said D.C. supply voltage; said second terminal of said ninth transistor is connected to said control terminal of said tenth transistor and connected to said first terminal of said D.C. supply voltage by means of a first constant current generator, and connected to an anode of a fifth diode; said first terminal of said ninth and tenth transistors and a cathode of said fifth diode are connected to said second terminal of said D.C. supply voltage, said second terminal of said tenth transistor is connected to said control terminals of said third, fourth and sixth transistors and connected to said cathode of said first diode; and wherein said timed enabling circuit means comprises: eleventh, twelfth, and thirteenth transistors, each having first, second and control terminals, said eleventh and twelfth transistors being of said first type of conductivity and said thirteenth transistor being of said second type of conductivity; said control terminal of said eleventh transistor is connected to said second terminal of said eighth transistor and to said cathode of said fourth diode; said first and second terminals of said eleventh transistor are respectively connected to said first terminal said D.C. supply voltage and to said control terminal of said twelfth transistor and further connected by means of a second constant current generator to said second terminal of said D.C. supply voltage; said control terminal of said twelfth transistor is also connected to a cathode of a sixth diode, an anode of said sixth diode being connected to said first terminal of said DC supply voltage; said first and second terminals of said twelfth transistor are respectively connected to said first terminal of said D.C. supply voltage and to both said control terminal of said thirteenth transistor and an anode of a seventh diode; a cathode of said seventh diode and said first terminal of said thirteenth transistor are connected to said second terminal of said D.C. supply voltage; said second terminal of said thirteenth transistor is also connected to said second terminal of said ninth transistor.

Claim 12

A circuit according to claim 9, wherein said eleventh and first transistors have approximately the same physical and electrical characteristics.

Claim 13

A circuit according to claim 1, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said rransistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 14

A circuit according to claim 2, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 15

A circuit according to claim 3, wherein each of said rransistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 16

A circuit according to claim 4, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 17

A circuit according to claim 5, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 18

A circuit according to claim 6, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 19

A circuit according to claim 7, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 20

A circuit according to claim 8, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 21

A circuit according to claim 9, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.

Claim 22

A circuit according to claim 10, wherein each of said transistors comprise bipolar transistors, wherein said first terminal, control terminal and second terminal of each of said transistors respectively comprise an emitter, a base and a collector of said bipolar transistor.