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US4547719A Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronous motor drive apparatus

Assignee: Fanuc Corp
•
Filing: 1983-01-25
•
Granted: 1985-10-15
•
Expires: 2003-01-25
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Abstract

Abstract To reduce adverse effects due to a dead zone in a pulse-width modulation circuit provided for avoiding short-circuiting in an inverter circuit, distortions of sine wave currents generated when low-frequency current commands are given, sound produced due to the excitation, and torque variations, a synchronous motor drive apparatus has been provided. The apparatus comprises a current detector circuit for detecting drive currents given to the synchronous motor, a difference output circuit for producing as outputs the differences between current commands given to the synchronous motor and the detected currents, a pulse-width modulation circuit for modulating signals indicative of the differences by way of pulse-duration modulation, an inverter circuit for driving the synchronous motor, a voltage detector circuit for detecting output voltages from output terminals of the inverter circuit, and a circuit for generating the differences between output voltages from the difference output circuit and the detected output voltages, whereby the synchronous motor can be driven by the outputs from the inverter circuit which is operated by voltage command values indicating the last-mentioned differences.

Inventors

  • 👤 Keiji Sakamoto
  • 👤 Shinji Seki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 14:00
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53875; H02P; H02P25/00; H02P25/02; H02P25/022; H02P25/03; H02M1/00; H02M1/38; H02M1/385

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 196 words
An apparatus for driving a synchronous motor, comprising: a current detector circuit for detecting drive currents applied to the synchronous motor; a current command circuit for producing current commands which drive the synchronous motor on the basis of a signal detected from an output side of the synchronous motor; a difference output circuit, operatively connected to said current detector circuit and said current command circuit, for producing as outputs first differences between the current commands and the detected drive currents; a pulse width modulation circuit, operatively connected to the motor, for producing inverter control signals; an inverter circuit, operatively connected to said pulse width modulation circuit and said current detector circuit, for producing phase voltages for driving the synchronous motor; and a voltage feedback loop comprising conversion means, operatively connected to said inverter circuit to receive the phase voltages applied to the motor, to said difference output circuit and to said pulse width modulation circuit, for converting the phase voltages to interphase voltages, for converting the interphase voltages to phase voltage signals, for combining the phase voltage signals with the first differences and for appling the combinations to said pulse width modulation circuit for controlling same.
Claim 2
Independent Claim 196 words
An apparatus for driving a synchronous motor, comprising: a current detector circuit for detecting drive currents applied to the synchronous motor; a current command circuit for producing current commands which drive the synchronous motor on the basis of a signal detected from an output side of the synchronous motor; a difference output circuit, operatively connected to said current detector circuit and said current command circuit, for producing as outputs first differences between the current commands and the detected drive currents; a pulse width modulation circuit, operatively connected to the motor, for producing inverter control signals; an inverter circuit, operatively connected to said pulse width modulation circuit and said current detector circuit, for producing phase voltages for driving the synchronous motor; and a voltage feedback loop comprising conversion means, operatively connected to said inverter circuit to receive the phase voltages applied to the motor, to said difference output circuit and to said pulse width modulation circuit, for converting the phase voltages to interphase voltages, for converting the interphase voltages to phase voltage signals, for combining the phase voltage signals with the first differences and for appling the combinations to said pulse width modulation circuit for controlling same.
Claim 3
Dependent Claim 91 words
An apparatus according to claim 1, wherein said conversion means comprises: interphase voltage detector circuits, operatively connected to said inverter circuit, for producing the interphase voltages between respective phases from the phase voltages produced by said inverter circuit; converter circuits in the respective phases, operatively connected to said interphae voltage detector circuits, for converting the interphase voltages into the phase voltage signals; and arithmetic circuits, operatively connected to said difference output circuit, said pulse width modulation circuit and said converter circuits, for subtracting the phase voltage signals from the first differences.
Claim 4
Dependent Claim 51 words
An apparatus according to claim 2, wherein each said interphase voltage detector circuit comprises interphase voltage detectors for detecting voltage differences between the phases and successive phases, and each said converter circuit comprises phase voltage computing circuits for producing as outputs the phase voltage signals from the difference between interphase voltages.
Claim 5
Dependent Claim 29 words
An apparatus according to claim 3, wherein each of said interphase voltage detectors comprises an input, an output, and a photocoupler by which said input and output are interconnected.
Claim 6
Dependent Claim 15 words
An apparatus according to claim 4, wherein said apparatus is driven by three-phase alternating currents.
Claim 7
Dependent Claim 105 words
An apparatus according to claim 2, wherein each of said interphase voltage detector circuits comprise: a first diode operatively connected to one phase of said inverter circuit; a second diode operatively connected to another phase of said inverter circuit; a coupling resistor operatively connected between said first and second diodes; a first photocoupler operatively connected to said first diode and said coupling resistor; a second photocoupler operatively connected to said second diode and said coupling resistor; a first output transistor operatively connected to said first photocoupler and said arithmetic circuits; and a second output transistor operatively connected to said second photocoupler and said arithmetic circuits.
Claim 8
Dependent Claim 14 words
An apparatus according to claim 2, wherein each converter circuit comprises an arithmetic circuit.
Claim 9
Dependent Claim 98 words
A synchronous motor control apparatus, comprising: inverter means for producing phase voltages which drive the motor; pulse width modulation means for controlling the inverter and providing a dead time between phase voltages; current command means for providing current control signals in dependence upon a difference between a current command and actual current supplied to the motor; and dead time reduction means for monitoring the phase voltages, reducing the dead time by producing interphase voltages and modifying the difference in dependence upon the interphase voltages, and applying the modified difference to said pulse width modulation means for controlling same.
Claim 10
Dependent Claim 98 words
A synchronous motor control apparatus, comprising: inverter means for producing phase voltages which drive the motor; pulse width modulation means for controlling the inverter and providing a dead time between phase voltages; current command means for providing current control signals in dependence upon a difference between a current command and actual current supplied to the motor; and dead time reduction means for monitoring the phase voltages, reducing the dead time by producing interphase voltages and modifying the difference in dependence upon the interphase voltages, and applying the modified difference to said pulse width modulation means for controlling same.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-10-14 1989-04-15 1989-10-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-10-14 1993-04-15 1993-10-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-10-14 1997-04-15 1997-10-15 $7700.00 Window Closed / Lapsed

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