Data transmission system with distributed microprocessors

Claim 2

A data link control system for plural stations, comprising: a transmission line coupled to said plural stations for transmitting data and signals; and a common request line for carrying a request signal which indicates the ability to be assigned to a master control function for supervising the data link, wherein said plural stations contains one node station and other node stations, at least one of which has the same configuration as said one node station, said one node station comprising: autoresponse means for receiving data from said transmission line in a reception mode and transmitting data of a predetermined format onto said transmission line in a transmission mode; control circuit means coupled to said common reuest line for generating said request signal so that said common request line is set to a busy status when said one node station requests to be assigned to the master control function; detecting circuit means coupled to said common request line for detecting the status of said common request line in accordance with the contents of said request signal; and microprocessor means coupled to said autoresponse means, control circuit means and detecting circuit means for restraining a search for finding out if any of said other node stations requests to be assigned to the master control function when said common request line is not in the busy status, and for assigning the master control function in accordance with a polling/selecting system when one or more of said other node stations request the master control function, said microprocessor means of said one node station supervising the data link when said one node station obtains the master control function, wherein said autoresponse means is responsive to a question regarding the assigning of the master control function delivered from one of the stations which has the master control function, but the receiving/transmitting operation of said autoresponse means is free from the operation of said microprocessor means.

Claim 3

A system according to claim 1 further comprising: a special request line coupled to said one and other node stations for carrying a special request signal having a priority over the request signal on said common request line; and a supervisor station coupled to said transmission line, common request line and special request line, said supervisor station including: supervisor autoresponse means for receiving data from said transmission line in a reception mode and transmitting data of a predetermined format onto said transmission line in a transmission mode; supervisor control circuit means coupled to said special request line for generating said special request signal so that said special request line is set to a busy status when said supervisor station requests to be assigned to the master control function; supervisor detecting circuit means for detecting the status of said special request line in accordance with the contenets of said special request signal, and detecting the status of said common request line in accordance with the contents of said request signal; and supervisor microprocessor means coupled to said supervisor autoresponse means, supervisor control circuit means and supervisor detecting circuit means, for restraining a search for finding out if any of said one and other node stations requests to be assigned to the master control function when said common request line is not in the busy status, for obtaining the master control function when said special request line is set in the busy status, and for assigning the master control function in accordance with a polling/selecting system when one or more of said one and other node stations request the master control funtion, said supervisor microprocessor means governing the data link when none of said one and other node stations obtains the master control function, wherein said supervisor autoresponse means is responsive to a question regarding the assigning of the master control function delivered from one of the stations which has the master control function, but the receiving/transmitting operation of said supervisor autoresponse means is free from the operation of said supervisor microprocessor means.

Claim 4

A system according to claim 2, wherein each of said one and other node stations includes: means coupled to said special request line and to said microprocessor means for detecting the status of said special request line in accordance with the contents of said special request signal, said microprocessor means assigning the master control function to said supervisor station when said special request line is set in the busy status.

Claim 5

A system according to claim 1, wherein said control circuit means includes: a switch circuit for changing the potential of said common request line between high and low levels, one of said high and low levels representing said request signal which indicates said busy status.

Claim 6

A system according to claim 4, wherein said detecting circuit means includes: an input port for sensing the potential of said common request line to detect the status thereof; and sensor circuit for sensing a change in the potential of said common request line to detect a change in the status thereof.

Claim 7

A system according to claim 2, wherein said supervisor control circuit means includes: a supervisor switch circuit for changing the potential of said special request line between high and low levels, one of said high and low levels representing said special request signal which indicates said busy status.

Claim 8

A system according to claim 6, wherein said supervisor detecting circuit means includes: a supervisor input port for sensing the potential of said special request line to detect the status thereof; and a supervisor sensor circuit for sensing a change in the potential of said special request line to detect a change in the status thereof.

Claim 9

A system according to claim 1, wherein said autoresponse means includes a communications interface for converting data on said transmission line into data of a format suitable to said microprocessor means, and converting data from said microprocessor means into data of a format suitable to said transmission line; and an autoresponse control circuit for effecting data exchanging with said transmission line via said communications interface.

Claim 10

A system according to claim 2, said supervisor autoresponse means including: a supervisor communications interface for converting data on said transmission line into data of a format suitable to said supervisor microprocessor means and converting data from said supervisor microprocessor means into data of a format suitable to said transmission line; and a supervisor autoresponse control circuit for effecting data exchanging with said transmission line via said supervisor communications interface.

Claim 11

A system according to claim 8, wherein said autoresponse means includes a memory for storing the data from said communications interface and delivering the stored data to said communications interface, and said autoresponse means further includes: a DMA controller coupled to said autoresponse control circuit and to said memory for connecting said memory to said transmission line when the data exchanging operation of said autoresponse control circuit is effected, the storing/delivering operation of said memory being free from the operation of said microprocessor means when said DMA controller connects said memory to said transmission line.

Claim 12

A system according to claim 9, wherein said supervisor autoresponse means includes a supervisor memory for storing the data from said supervisor communications interface and delivering the stored data to said supervisor communications interface, and said supervisor autoresponse means further includes: a supervisor DMA controller coupled to said supervisor autoresponse control circuit and to said supervisor memory for connecting said supervisor memory to said transnmission line when the data exchanging operation of said supervisor autoresponse control circuit is effected, the storing/delivering operation of said supervisor memory being free from the operation of said supervisor microprocessor means when said supervisor DMA controller connects said supervisor memory to said transmission line.

Claim 13

A system acording to claim 10, wherein said autoresponse control circuit includes: a judging circuit for determining whether or not an autoresponse mode is established; and a DMA control generator coupled to said judging circuit and to said DMA controller for effecting the connecting operation of said DMA controller when said autoresponse mode is established.

Claim 14

A system according to claim 11 wherein said supervisor autoresponse control circuit includes: a supervisor judging circuit for determining whether or not a supervisor autoresponse mode is established; and a supervisor DMA control generator coupled to said supervisor judging circuit and to said supervisor DMA controller for effecting the connecting operation of said supervisor DMA controller when said supervisor autoresponse mode is established.

Claim 15

A system according to claim 12, wherein said autoresponse control circuit further includes: a receiving status check circuit coupled to said DMA control generator for detecting whether or not reception of data from a transmission line is completed without error, said DMA control generator being effected only when said receiving status check circuit detects that the reception is completed without error.

Claim 16

A system according to claim 13, wherein said supervisor autoresponse control circuit further inludes: a supervisor receiving status check circuit coupled to said supervisor DMA control generator for detecting whether or not reception of data from a transmission line is completed without error, said supervisor DMA control generator being effected only when said supervisor receiving status check circuit detects that the reception is completed without error.

Claim 17

A system according to claim 12, wherein said autoresponse control circuit further includes: an interrupt generator coupled to said judging circuit and to said microprocessor means, for interrupting the operation of said microprocessor means when said judging circuit determines that the autoresponse mode is not established.

Claim 18

A system according to claim 13, wherein said supervisor autoresponse control circuit further includes: a supervisor interrupt generator coupled to said supervisor judging circuit and to said supervisor microprocessor means for interrupting the operation of said supervisor microprocessor means when said supervisor judging circuit determines that the supervisor autoresponse mode is not established.

Claim 19

A system according to claim 16, wherein said interrupt generator is coupled to said judging circuit and to said receiving status check circuit and said interrupt generator interrupts the operation of said microprocessor means only when said receiving status check circuit detects that the reception is completed without error and said judging circuit determines that the autoresponse mode is not established.

Claim 20

A system according to claim 17, wherein said supervisor interrupt generator is coupled to said supervisor judging circuit and to said supervisor receiving status check circuit, and said supervisor interrupt generator interrupts the operation of said supervisor microprocessor means only when said supervisor receiving status check circuit detects that the reception is completed without error and said supervisor judging circuit determines that the supervisor autoresponse mode is not established.

Claim 21

A system according to claim 1, wherein all of said other node stations have the same configuration as said one node station.