US4546350A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Display apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1982-05-04
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Granted: 1985-10-08
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Expires: 2002-05-04
Abstract
Abstract An improved timing signal generating circuit for use in a raster-scanning CRT display apparatus. The circuit provides timing signals including memory control signals and clocks for the screen memory which stores data for characters and graphic patterns to be displayed on the CRT display unit, the CRT control circuit which supplies the synchronizing signal to the display unit and supplies the display address signal to the screen memory, and the processing circuit which reads and writes the screen memory. The timing signal generating circuit comprises a counter for dividing the frequency of the original oscillation signal, a first memory device which receives at its address terminal the output of the counter, and a second memory device which receives at its input terminal the output of the first memory device and stores it in response to the original oscillation signal whereby to provide outputs as the timing signals.
Inventors
- 👤 Kazuyuki Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:38
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/18
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
269 words
A display apparatus comprising: a display means including a cathode ray tube (CRT) of the raster scanning type; a screen memory for storing data to be displayed on said display means; a CRT control circuit for supplying a synchronizing signal to said display means and supplying a display address signal which corresponds to a display position on the CRT screen to said screen memory; a processing circuit for reading to and writing from said screen memory; and a timing signal generating circuit for providing timing signals including (a) an operating clock signal for said CRT control circuit, (b) a clock signal for said processing circuit and (c) control signals for timing the read-out of display data from said screen memory, said timing signal generating circuit comprising means for dividing a frequency of an applied oscillating signal to produce a plurality of different frequency signals, memory means having address input terminals and data output terminals, said memory means storing data representing said timing signals and receiving at respective address input terminals said plurality of different frequency signals, said memory means supplying said stored data at said output terminals in response to said plurality of different frequency signals applied to said address input terminals, and a latching means for eliminating changes in the data at said output terminals of said memory means when said frequency dividing means changes state by storing data at the data output terminals of said memory means and by supplying said stored data to said CRT control circuit, said processing circuit and said screen memory, respectively, as said timing signals in response to said applied oscillating signal.
Claim 2
Dependent Claim
269 words
A display apparatus comprising: a display means including a cathode ray tube (CRT) of the raster scanning type; a screen memory for storing data to be displayed on said display means; a CRT control circuit for supplying a synchronizing signal to said display means and supplying a display address signal which corresponds to a display position on the CRT screen to said screen memory; a processing circuit for reading to and writing from said screen memory; and a timing signal generating circuit for providing timing signals including (a) an operating clock signal for said CRT control circuit, (b) a clock signal for said processing circuit and (c) control signals for timing the read-out of display data from said screen memory, said timing signal generating circuit comprising means for dividing a frequency of an applied oscillating signal to produce a plurality of different frequency signals, memory means having address input terminals and data output terminals, said memory means storing data representing said timing signals and receiving at respective address input terminals said plurality of different frequency signals, said memory means supplying said stored data at said output terminals in response to said plurality of different frequency signals applied to said address input terminals, and a latching means for eliminating changes in the data at said output terminals of said memory means when said frequency dividing means changes state by storing data at the data output terminals of said memory means and by supplying said stored data to said CRT control circuit, said processing circuit and said screen memory, respectively, as said timing signals in response to said applied oscillating signal.
Claim 3
Dependent Claim
16 words
A display apparatus according to claim 1 wherein said memory means is a read only memory.
Claim 4
Dependent Claim
16 words
A display apparatus according to claim 1 wherein said memory means is a random access memory.
Claim 5
Dependent Claim
32 words
A display apparatus according to claim 1 wherein at least one of said address input terminals is connected to a switch means for applying a signal of a selected logic level thereto.
Claim 6
Dependent Claim
129 words
A display apparatus according to claim 1, further comprising: address selector means for receiving the display address signal supplied from said CRT control circuit and for receiving a CPU address signal supplied from said processing circuit and for selectively transmitting the received address signals to respective address terminals of said screem memory in response to one of said timing signals provided by said timing signal generating circuit; a character generator having address terminals for receiving display data signals from said screen memory and for generating parallel character data signals; and a parallel to serial converter, responsive to at least one of said timing signals for receiving the character data signals and converting the received data signals into a serial video signal to be applied to said cathode ray tube.
Claim 7
Dependent Claim
15 words
A display apparatus according to claim 1 wherein said screen memory is a dynamic memory.
Claim 8
Dependent Claim
141 words
A timing signal generating circuit for generating timing signals for use in operating a display apparatus comprising: means for dividing a frequency of an applied oscillating signal to produce at a plurality of different frequency signals; memory means having address input terminals and data output terminals, said memory means storing data representing said timing signals and receiving at respective address input terminals said plurality of different frequency signals, said memory means supplying said stored data representing said timing signals at said output terminals in response to said plurality of different frequency signals applied to said address input termimals; and, latching means for eliminating changes in the data at said output terminals of said memory means when said frequencey dividing means changes state by storing data at the date output terminals of said memory means in response to said applied oscillating signal.
Claim 9
Dependent Claim
141 words
A timing signal generating circuit for generating timing signals for use in operating a display apparatus comprising: means for dividing a frequency of an applied oscillating signal to produce at a plurality of different frequency signals; memory means having address input terminals and data output terminals, said memory means storing data representing said timing signals and receiving at respective address input terminals said plurality of different frequency signals, said memory means supplying said stored data representing said timing signals at said output terminals in response to said plurality of different frequency signals applied to said address input termimals; and, latching means for eliminating changes in the data at said output terminals of said memory means when said frequencey dividing means changes state by storing data at the date output terminals of said memory means in response to said applied oscillating signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |