US4539693A
Expired / Lapsed
US
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Bit synchronization arrangement for a data modem or data receiver
Assignee: Telecommunications Radioelectriques et Telephoniques SA TRT
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Filing: 1983-04-25
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Granted: 1985-09-03
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Expires: 2003-04-25
Abstract
Abstract In an asynchronous transmission mode, the bit synchronization arrangement receives data signals in the form of binary pulse trains (at A). It includes an oscillator (3) whose output signal (at C) has a frequency F OS approximately equal to twice the binary rate of the pulse trains and a transition detector (1, 22) which supplies a calibrated voltage pulse (at B 2 ) at each data signal transition. The oscillator supplies a triangular internal signal (at D) at the frequency F OS and a phase correction circuit (2) is provided to reduce the algebraic value of the slope of this signal during each calibrated pulse so as to produce a predetermined constant advancing or delaying phase shift according as the calibrated pulse occurs during a negative or a positive ramp of this signal.
Inventors
- 👤 Robert Boudault
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:17
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03K; H03K4/00; H03K4/06; H03K4/066
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
170 words
A bit synchronization apparatus for furnishing an output signal synchronized to asynchronously received data signals constituted by binary pulse trains having a base frequency and detectable transitions between binary states, comprising, transition detector means for receiving said data signals and generating a correction pulse having a predetermined duration in response to each transition of said data signals; oscillator means for generating a sequence of triangular signals each having a first and second side respectively having a finite first and second slope, said sequence of triangular signals having a frequency corresponding to said base frequency whereby an instantaneous phase shift exists between said received data signals and said triangular signals; phase correction means interconnected between said transition detector means and said oscillator means for changing said first or said second slope in a direction decreasing said phase shift during occurrence of each of said correction pulses when said correction pulse occurs during said first or second side, respectively; and means for generating said output signals in synchronism with said triangular signals.
Claim 2
Dependent Claim
170 words
A bit synchronization apparatus for furnishing an output signal synchronized to asynchronously received data signals constituted by binary pulse trains having a base frequency and detectable transitions between binary states, comprising, transition detector means for receiving said data signals and generating a correction pulse having a predetermined duration in response to each transition of said data signals; oscillator means for generating a sequence of triangular signals each having a first and second side respectively having a finite first and second slope, said sequence of triangular signals having a frequency corresponding to said base frequency whereby an instantaneous phase shift exists between said received data signals and said triangular signals; phase correction means interconnected between said transition detector means and said oscillator means for changing said first or said second slope in a direction decreasing said phase shift during occurrence of each of said correction pulses when said correction pulse occurs during said first or second side, respectively; and means for generating said output signals in synchronism with said triangular signals.
Claim 3
Dependent Claim
97 words
Apparatus as set forth in claim 1, wherein said oscillator means comprises an operational amplifier having an operational amplifier output, an inverting input and a capacitor connected to said output and said inverting input; wherein said output signal generating means comprises a bistable circuit having a bistable circuit output; further comprising a first resistor connected to said bistable circuit output and said inverting input; and wherein said phase correction means comprises a second resistor substantially equal in resistance to said first resistor and connected between said transition detector means and said inverting input of said operational amplifier.
Claim 4
Dependent Claim
48 words
Apparatus as set forth in claim 2, wherein said first slope has a predetermined magnitude and said second slope has a magnitude equal to said predetermined magnitude; and wherein said first resistor has a predetermined resistance and said second resistor has a resistance equal to said predetermined resistance.
Claim 5
Dependent Claim
38 words
Apparatus as set forth in claim 2, wherein each of said pulse trains comprises a first pulse; further comprising rapid synchronization means connected to said oscillator means for completely phase resetting said oscillator means during said first pulse.
Claim 6
Dependent Claim
52 words
Apparatus as set forth in claim 4, wherein said rapid synchronization means comprises resistive discharge circuit means, interruptor means connecting said discharge circuit means to said oscillator means when closed, and means connecting said interruptor means to said transition detector means so that said interruptor means is closed during said correction pulse.
Claim 7
Dependent Claim
45 words
Apparatus as set forth in claim 5, further comprising means for generating a data detection signal indicative of presence of said pulse trains, and means for applying said data detection signal to said interruptor means, to maintain said interruptor means open after said first pulse.
Claim 8
Dependent Claim
79 words
Apparatus as set forth in claim 6, wherein each of said pulse trains commences with a first pulse; further comprising means for generating a data detection signal prior to occurrence of said first pulse, a flip-flop having a clock input connected to receive said data detection signal, a set input connected to receive said correction pulse and a flip-flop output connected to said interruptor means so that said interruptor means is closed during said first pulse and opened thereafter.
Claim 9
Dependent Claim
36 words
Apparatus as set forth in claim 1, wherein said first slope of said first side of said triangular signal has a predetermined magnitude, and wherein said second slope has a magnitude less than said predetermined magnitude.
Claim 10
Dependent Claim
44 words
Apparatus as set forth in claim 8, wherein said operational amplifier further has a direct input; and wherein said means for changing said slopes of said first and second sides comprises means for changing the voltage at said direct input of said operational amplifier.
Claim 11
Dependent Claim
15 words
Apparatus as set forth in claim 1, wherein said apparatus is manufactured in CMOS Technology.
Claim 12
Dependent Claim
16 words
Apparatus as set forth in claim 1, wherein said apparatus manufactured by thick-film hybrid circuit technology.
Claim 13
Dependent Claim
38 words
Apparatus as set forth in claim 1, wherein said first side and second sides each have a time duration; and wherein said predetermined duration of said correction pulse is substantially less than said time duration of said sides.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |