US4539658A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Renesas Technology Corp
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Filing: 1984-08-08
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Granted: 1985-09-03
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Expires: 2004-08-08
Abstract
Abstract A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
Inventors
- 👤 Katsuhiro Shimohigashi
- 👤 Hiroo Masuda
- 👤 Kunihiko Ikuzaki
- 👤 Hiroshi Kawamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4096; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/164
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
81 words
A semiconductor memory comprising: a plurality of pairs of data lines; differential amplifiers, each of which amplifies a difference between signal levels appearing on each pair of data lines; word lines, each of which is arranged so as to intersect with each pair of data lines; and precharging circuits, each of which sets each pair of data lines at a potential intermediate between binary signal levels to be stored in memory cells, before operation of the corresponding differential amplifier is started.
Claim 2
Dependent Claim
81 words
A semiconductor memory comprising: a plurality of pairs of data lines; differential amplifiers, each of which amplifies a difference between signal levels appearing on each pair of data lines; word lines, each of which is arranged so as to intersect with each pair of data lines; and precharging circuits, each of which sets each pair of data lines at a potential intermediate between binary signal levels to be stored in memory cells, before operation of the corresponding differential amplifier is started.
References Cited (Backward Citations)
US4417328A
Cited
US4451906A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |