US4539552A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital-to-analog converter
Assignee: Nokia Bell Labs
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Filing: 1982-09-10
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Granted: 1985-09-03
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Expires: 2002-09-10
Abstract
Abstract A digital-to-analog signal converter (1000) provides an analog output signal by subtracting bit currents reflecting a digital input signal from a constant current source (1004, 1018-1022) at a current summer (1003), with the difference current being applied to a constant load. The subtracting of the current, rather than switching the current, avoids the modulation of an associated power source since the total current demand remains the same. In that low power operation is possible, the converter is particularly suited for use in an arrangement where only a low level of operating current is available from a power source.
Inventors
- 👤 Paul C. Davis
- 👤 Raymond G. Jackson
- 👤 Joseph J. Nahas
- 👤 Dale H. Nelson
- 👤 DeWitt G. Ong
- 👤 Brian A. Wittman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:56
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/26; H04M1/30; H04M1/50; H04M1/505
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
177 words
A digital-to-analog converter comprising input circuit connections (861, 862, 761, 762) for receiving a plurality of binary input signals, and means responsive to the binary input signals for producing an analog output signal at an output circuit connection (1001), the magnitude of the analog output signal being representative of the binary input signals, characterized in that: the converter includes a constant current generator (1004, 1018-1022) connected to a power source, the constant current generator comprising a current mirror with a first transistor (1018) and a second transistor (1004) and wherein a fixed constant current in the first transistor is repeated in the second transistor; the means for producing the analog output signal is comprised of means for subtracting a source current reflective of the binary input signals from the current in the second transistor at a first current summer (1003), the amount subtracted being determined by the received binary input signals; and the converter provides a constant total current demand from the power source while receiving any one or combination of the plurality of binary input signals.
Claim 2
Dependent Claim
177 words
A digital-to-analog converter comprising input circuit connections (861, 862, 761, 762) for receiving a plurality of binary input signals, and means responsive to the binary input signals for producing an analog output signal at an output circuit connection (1001), the magnitude of the analog output signal being representative of the binary input signals, characterized in that: the converter includes a constant current generator (1004, 1018-1022) connected to a power source, the constant current generator comprising a current mirror with a first transistor (1018) and a second transistor (1004) and wherein a fixed constant current in the first transistor is repeated in the second transistor; the means for producing the analog output signal is comprised of means for subtracting a source current reflective of the binary input signals from the current in the second transistor at a first current summer (1003), the amount subtracted being determined by the received binary input signals; and the converter provides a constant total current demand from the power source while receiving any one or combination of the plurality of binary input signals.
Claim 3
Dependent Claim
50 words
The digital-to-analog converter of claim 1 further characterized in that the output of the first current summer is connected through a resistive element (1002) to a second reference potential, and the analog output signal for the output circuit connection's being obtained solely from the voltage developed across the resistive element.
Claim 4
Dependent Claim
90 words
The digital-to-analog converter of claim 2 further characterized in that each one of a plurality of transistor switches (1006, 1007, 1009, 1010) is connected to a first side of one of a plurality of current controlling resistive elements (1012, 1013, 1015, 1016) and provides a low-resistance current path for the resistive elements upon receiving an associated binary input signal and a high resistance current path in the absence of the associated binary input signal, the input circuit connection being the control node of each one of the plurality of switches.
Claim 5
Dependent Claim
126 words
The digital-to-analog converter of claim 1 further characterized in that a first side of each one of a plurality of switches (1006, 1007, 1009, 1010) is commonly connected to a reference potential (118), and the second side of each one of the plurality of switches is respectively connected to a first side of one of a plurality of current controlling resistive elements (1012, 1013, 1015, 1016), the plurality of resistive elements being commonly connected to a first side of a second current summer (1005), the second side of the second current summer providing the source current for subtracting at the first current summer, and a common reference voltage being provided to the constant current generator and to the switched resistive elements through the second current summer.
Claim 6
Dependent Claim
48 words
The digital-to-analog converter of claim 4 further characterized in and including means (1008, 1011) connected to input circuit connections (763, 863) for substituting a dc level output signal equivalent in the absence of a binary input signal to the digital-to-analog converter for maintaining a constant average output level.
Claim 7
Dependent Claim
70 words
The digital-to-analog converter of claim 5 wherein the means for substituting a dc level output signal equivalent comprises at least one switch (1008) for providing a low-resistance current path for a current controlling resistive element (1014) upon receiving an activation signal from the associated input circuit connection and a high-resistance circuit path in the absence of the activation signal, the input circuit connection being the control node for the switch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |