US4539529A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor amplifier circuit
Assignee: Siemens AG
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Filing: 1983-09-15
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Granted: 1985-09-03
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Expires: 2003-09-15
Abstract
Abstract A semiconductor amplifier circuit includes first and second operational amplifiers, and first and second voltage dividers connected between the outputs of the first and second operational amplifiers, respectively, and a reference potential source. First and second resistors are connected between the divider point of the first and second voltage dividers, respectively, and the inverting input of the first and second operational amplifiers, respectively, forming real negative feedbacks. A first signal input terminal of the amplifier circuit is connected to the non-inverting input of the first and second operational amplifiers, respectively. A third common voltage divider is connected between the reference potential source and a supply potential source. A common intermediate resistor is connected to the divider point of the common voltage divider, and first and second supply resistors are connected in series with the intermediate resistor. The first and second supply resistors are connected between the intermediate resistor and the non-inverting input of the first and second operational amplifiers, respectively. The first resistor has a resistance substantially equal to the sum of the resistance of the first supply resistor and twice the resistance of the intermediate resistor. The second resistor has a resistance substantially equal to the sum of the resistance of the second supply resistor and twice the resistance of the intermediate resistor.
Inventors
- 👤 Michael Lenz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:40
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/68; H03F1/00; H03F1/32; H03F1/3217; H03F3/45; H03F3/45071
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
327 words
Semiconductor amplifier circuit, comprising first and second operational amplifiers each having an inverting input, a non-inverting input and an output, a reference potential source, a supply potential source, a first voltage divider formed of two series-connected resistors connected between said output of said first operational amplifier and said reference potential source, a second voltage divider formed of two series-connected resistors connected between said output of said second operational amplifier and said reference potential source, each of said voltage dividers having a divider point between said resistors thereof, a first resistor connected between said divider point of said first voltage divider and said inverting input of said first operational amplifier forming a real negative feedback, a second resistor connected between said divider point of said second voltage divider and said inverting input of said second operational amplifier forming a real negative feedback, a first signal input terminal of the amplifier circuit connected to said non-inverting input of said first operational amplifier, a second signal input terminal of the amplifier circuit connected to said non-inverting input of said second operational amplifier, a third common voltage divider connected between said reference potential source and said supply potential source, said common voltage divider including two resistors defining a divider point therebetween, a common intermediate resistor connected to said divider point of said common voltage divider, and first and second supply resistors connected in series with said intermediate resistor, said first supply resistor being connected between said intermediate resistor and said non-inverting input of said first operational amplifier, said second supply resistor being connected between said intermediate resistor and said non-inverting input of said second operational amplifier, said first resistor having a resistance substantially equal to the sum of the resistance of said first supply resistor and twice the resistance of said intermediate resistor, and said second resistor having a resistance substantially equal to the sum of the resistance of said second supply resistor and twice the resistance of said intermediate resistor.
Claim 2
Dependent Claim
327 words
Semiconductor amplifier circuit, comprising first and second operational amplifiers each having an inverting input, a non-inverting input and an output, a reference potential source, a supply potential source, a first voltage divider formed of two series-connected resistors connected between said output of said first operational amplifier and said reference potential source, a second voltage divider formed of two series-connected resistors connected between said output of said second operational amplifier and said reference potential source, each of said voltage dividers having a divider point between said resistors thereof, a first resistor connected between said divider point of said first voltage divider and said inverting input of said first operational amplifier forming a real negative feedback, a second resistor connected between said divider point of said second voltage divider and said inverting input of said second operational amplifier forming a real negative feedback, a first signal input terminal of the amplifier circuit connected to said non-inverting input of said first operational amplifier, a second signal input terminal of the amplifier circuit connected to said non-inverting input of said second operational amplifier, a third common voltage divider connected between said reference potential source and said supply potential source, said common voltage divider including two resistors defining a divider point therebetween, a common intermediate resistor connected to said divider point of said common voltage divider, and first and second supply resistors connected in series with said intermediate resistor, said first supply resistor being connected between said intermediate resistor and said non-inverting input of said first operational amplifier, said second supply resistor being connected between said intermediate resistor and said non-inverting input of said second operational amplifier, said first resistor having a resistance substantially equal to the sum of the resistance of said first supply resistor and twice the resistance of said intermediate resistor, and said second resistor having a resistance substantially equal to the sum of the resistance of said second supply resistor and twice the resistance of said intermediate resistor.
Claim 3
Dependent Claim
44 words
Semiconductor amplifier circuit according to claim 1, wherein said first and second operational amplifiers are alike in construction and rating, said resistors of said first and second voltage dividers are equal, said first and second resistors are equal, and said supply resistors are equal.
Claim 4
Dependent Claim
32 words
Semiconductor amplifier circuit according to claim 1, including another input signal terminal and another resistor connected between said other input signal terminal and said inverting input of one of said operational amplifiers.
Claim 5
Dependent Claim
32 words
Semiconductor amplifier circuit according to claim 2, including another input signal terminal and another resistor connected between said other input signal terminal and said inverting input of one of said operational amplifiers.
Claim 6
Dependent Claim
33 words
Semiconductor amplifier circuit according to claim 3, wherein said other resistor is connected to said inverting input of said first operational amplifier and has a resistance value substantially equal to said first resistor.
Claim 7
Dependent Claim
33 words
Semiconductor amplifier circuit according to claim 4, wherein said other resistor is connected to said inverting input of said first operational amplifier and has a resistance value substantially equal to said first resistor.
Claim 8
Dependent Claim
47 words
Semiconductor amplifier circuit according to claim 1, wherein said first and second operational amplifiers, said resistors of said first, second and third common voltage dividers, said first and second resistors, said first and second supply resistors, and said intermediate resistor are monolithically combined in a single chip.
References Cited (Backward Citations)
US4254380A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |