Patent US6728719B1 successfully refreshed from Google Patents.
US4536880A
Expired / Lapsed
US
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Digital DPCM-coder having a high processing speed
Assignee: Siemens AG
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Filing: 1983-08-16
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Granted: 1985-08-20
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Expires: 2003-08-16
Abstract
Abstract In an improved digital DPCM-coder having a high calculating speed, a second quantizer is provided which is supplied with a DPCM-signal determined in a calculating loop, and which emits from its output a quantized DPCM-signal multiplied by a prediction factor. With the improved coder, one calculating operation less is required, and the coder can process a higher PCM-data rate at a constant calculating speed of the components.
Inventors
- 👤 Hans-Joachim Grallert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:37
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/3002; H03M7/3044
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
197 words
A digital DPCM-coder having a high processing speed with fewer calculating operations, comprising: an adder having first and second inputs and an output; a subtractor having first and second inputs and an output; a multiplier means having an input and an output; a first quantizer means having an input and output; a second quantizer means having an input and output; a PCM signal input connecting to the first input of the subtractor; the output of the subtractor being connected to the input of the first quantizer means, said first quantizer means outputting quantized DPCM-signals; a calculating loop means connected between the output of the subtractor and the second input of the subtractor, said calculating loop means determining an estimated value which is fed to said subtractor second input; and said calculator loop means comprising the second quantizer means whose output is connected to the first input of the adder, the output of the adder connecting to the input of the multiplier means which multiplies with a prediciton factor A, the output of the multiplier means connecting to the second input of the adder, and the output of the adder connecting to the second input of the subtractor.
Claim 2
Dependent Claim
197 words
A digital DPCM-coder having a high processing speed with fewer calculating operations, comprising: an adder having first and second inputs and an output; a subtractor having first and second inputs and an output; a multiplier means having an input and an output; a first quantizer means having an input and output; a second quantizer means having an input and output; a PCM signal input connecting to the first input of the subtractor; the output of the subtractor being connected to the input of the first quantizer means, said first quantizer means outputting quantized DPCM-signals; a calculating loop means connected between the output of the subtractor and the second input of the subtractor, said calculating loop means determining an estimated value which is fed to said subtractor second input; and said calculator loop means comprising the second quantizer means whose output is connected to the first input of the adder, the output of the adder connecting to the input of the multiplier means which multiplies with a prediciton factor A, the output of the multiplier means connecting to the second input of the adder, and the output of the adder connecting to the second input of the subtractor.
Claim 3
Dependent Claim
216 words
A digital DPCM-coder having a high processing speed with fewer calculating operations, comprising: an adder having first and second inputs and an output; a subtractor having first and second inputs and an output; a multiplier means having an input and an output; a quantizer unit containing first and second quantizer means; the first quantizer means having an input and output; the second quantizer means having the same input as the first quantizer means and an output; a PCM signal input connecting to the first input of the subtractor; the output of the subtractor being connected to the input of the first and second quantizer means, said first quantizer means outputting quantized DPCM-signals; a calculating loop means connected between the output of the subtractor and the second input of the subtractor, said calculating loop means determining an estimated value which is fed to said subtractor second input; and said calculator loop means comprising the second quantizer means whose output is connected to the first input of the adder, the output of the adder connecting to the first input of the multiplier means which multiplies with a prediction factor A, the output of the multiplier means connecting to the second input of the adder, and the output of the adder connecting to the second input of the subtractor.
Claim 4
Dependent Claim
216 words
A digital DPCM-coder having a high processing speed with fewer calculating operations, comprising: an adder having first and second inputs and an output; a subtractor having first and second inputs and an output; a multiplier means having an input and an output; a quantizer unit containing first and second quantizer means; the first quantizer means having an input and output; the second quantizer means having the same input as the first quantizer means and an output; a PCM signal input connecting to the first input of the subtractor; the output of the subtractor being connected to the input of the first and second quantizer means, said first quantizer means outputting quantized DPCM-signals; a calculating loop means connected between the output of the subtractor and the second input of the subtractor, said calculating loop means determining an estimated value which is fed to said subtractor second input; and said calculator loop means comprising the second quantizer means whose output is connected to the first input of the adder, the output of the adder connecting to the first input of the multiplier means which multiplies with a prediction factor A, the output of the multiplier means connecting to the second input of the adder, and the output of the adder connecting to the second input of the subtractor.
Claim 5
Dependent Claim
214 words
A digital DPCM-coder having a high processing speed with fewer calculating operations, comprising: an adder having first and second inputs and an output; a subtractor having first and second inputs and an output; a first multiplier means having an input and an output; a second multiplier means having an input and output; a quantizer means having an input and output; a PCM signal input connecting to the first input of the subtractor; the output of the subtractor being connected to the input of the first multiplier means, said first multiplier means outputting quantized DPCM-signals; a calculating loop means connected between the output of the subtractor and the second input of the subtractor, said calculating loop means determining an estimated value which is fed to said subtractor second input; and said calculator loop means comprising the second quantizer means whose output is connected to the first input of the adder, the output of the adder connecting to the input of the first multiplier means which multiplies with a prediction factor A, the output of the first multiplier means connecting to the second input of the adder, the output of the adder connecting to the second input of the subtractor, and the second multiplier means multiplying by an inverse value 1/A of the prediction factor A.
Claim 6
Dependent Claim
214 words
A digital DPCM-coder having a high processing speed with fewer calculating operations, comprising: an adder having first and second inputs and an output; a subtractor having first and second inputs and an output; a first multiplier means having an input and an output; a second multiplier means having an input and output; a quantizer means having an input and output; a PCM signal input connecting to the first input of the subtractor; the output of the subtractor being connected to the input of the first multiplier means, said first multiplier means outputting quantized DPCM-signals; a calculating loop means connected between the output of the subtractor and the second input of the subtractor, said calculating loop means determining an estimated value which is fed to said subtractor second input; and said calculator loop means comprising the second quantizer means whose output is connected to the first input of the adder, the output of the adder connecting to the input of the first multiplier means which multiplies with a prediction factor A, the output of the first multiplier means connecting to the second input of the adder, the output of the adder connecting to the second input of the subtractor, and the second multiplier means multiplying by an inverse value 1/A of the prediction factor A.
References Cited (Backward Citations)
US4468790A
Cited
US4470146A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-19 | 1989-02-18 | 1989-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-19 | 1993-02-18 | 1993-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-19 | 1997-02-18 | 1997-08-20 | $7700.00 | Window Closed / Lapsed |