Sampling frequency conversion device

Claim 1

A sampling frequency conversion device for converting an input digital signal with a sampling frequency (M samples/second) and each sample having n quantization bits, to an output digital signal with sampling frequency (N samples/second) and each sample having n quantization bits, where M and N are prime numbers, comprising; (a) parallel shift registers each having bit length P+n, where P is an odd number equal to or larger than M, for accepting an input signal which has n bits, according to a timing of an input signal; (b) an address converter for providing P bits of output signal for each of said parallel shift registers for every shift operation of said shift registers; (c) N groups of ROMs storing ##EQU9## at an address designated by the output of said address converter, each group of said ROMs having [n/N]+1 number of ROMs, where K is an integer designating a sampling point, m is an integer designating a filter coefficient, h m is a coefficient of a filter, a i is a possible combination of addresses provided by P bits, and [ ] is a Gauss' symbol; (d) a shift register adder with the bit length 2n for providing an accumulation of the output of said ROMs with shift operation; and (e) an output gate coupled with an output of said shift register adder for providing a converted output signal; (f) a buffer memory for storing output of said output gate and providing converted sampled pulses with desired repetition frequency.