US4535452A
Expired / Lapsed
US
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Multi-modem variable port demultiplexer synchronization adapter
Assignee: Paradyne Corp
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Filing: 1984-02-29
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Granted: 1985-08-13
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Expires: 2004-02-29
Abstract
Abstract This invention discloses a demultiplexer with a first memory element for storing received data bits, a second memory element having individual cells connected to individual remote units (i.e. parallel output) and a logic unit for transferring the appropriate bits from the first to the second memory element in accordance with the received signal configuration. The enabling signal for the second memory element is derived from the demultiplex sync signal.
Inventors
- 👤 Terrel W. Sandberg
- 👤 Stanley Bottoms
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:20
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1647
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
93 words
In a digital communication system adapted to transmit multi-valued signals which are modulated to provide a demultiplex synchronizing signal, a demultiplexer comprising: a first memory element for storing received data bits said signals having a preselected configuration; a second memory element for transferring received data to several remote units in accordance with said demultiplex synchronizing signal; configuration control means for generating a command signal indicative of said signal configuration; and a logic array without memory for transferring from said first memory element to a second memory element in response to said command signal.
Claim 2
Dependent Claim
93 words
In a digital communication system adapted to transmit multi-valued signals which are modulated to provide a demultiplex synchronizing signal, a demultiplexer comprising: a first memory element for storing received data bits said signals having a preselected configuration; a second memory element for transferring received data to several remote units in accordance with said demultiplex synchronizing signal; configuration control means for generating a command signal indicative of said signal configuration; and a logic array without memory for transferring from said first memory element to a second memory element in response to said command signal.
Claim 3
Dependent Claim
37 words
The demultiplexer of claim 1 further comprising means for generating a second synchronizing signal for enabling said second memory unit, said second synchronizing signal being dependent on the rate of received signal and the demultiplex synchronizing signal.
Claim 4
Dependent Claim
18 words
The demultiplexer of claim 2 wherein said means for generating said second synchronizing signal comprises a phase-locked loop.
Claim 5
Dependent Claim
15 words
The demultiplexer of claim 1 wherein said first and second memory elements are shift registers.
Claim 6
Dependent Claim
15 words
The demultiplexer of claim 4 wherein said first memory element is a serial-in/parallel-out shift register.
Claim 7
Dependent Claim
13 words
The demultiplexer of claim 4 wherein said logic array comprises a logic matrix.
Claim 8
Dependent Claim
24 words
The demultiplexer of claim 4 wherein said logic array comprises discrete digital logic elements selected from a group consisting of NAND and NOR gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-12 | 1989-02-11 | 1989-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-12 | 1993-02-11 | 1993-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-12 | 1997-02-11 | 1997-08-13 | $7700.00 | Window Closed / Lapsed |