Line synchronizing circuit for a picture display devices and picture display device comprising such a circuit

Claim 1

A line synchronizing circuit for a picture display device, comprising a control loop for controlling the frequency and/or the phase of a line oscillator, said control loop including means for applying an incoming line synchronizing signal and a reference signal generated by the oscillator to a phase discriminator for determining the phase difference between the applied signals, and a low-pass filter for smoothing the output signal of the phase discriminator and for applying the smoothed output signal to the oscillator for controlling this oscillator, the circuit also comprising a coincidence detector for determining the phase difference between the incoming line synchronizing signal and the reference signal, and means coupled to said coincidence detector for switching elements of the control loop when said phase difference is less than a predetermined value for bringing the loop from a first into a second state, respectively, in which second state the loop gain and the pull in rate, respectively, have a higher value than in the first state, characterized in that said switching means comprises: a level detector for comparing the output signal of the coincidence detector with a first reference level which indicates the presence of an incoming line synchronizing signal but no coincidence, and for bringing the control loop into the second state until said output signal reaches the first reference level, and a signal prolonging element coupled to said level detector for subsequently maintaining the control loop in the said second state during a predetermined period of time.