A.C. Solid state relay circuit and structure

Claim 2

A solid state a.c. relay comprising first and second thyristors each having respective anode and cathode electrodes and a respective gate circuit; each of said thyristors being formed in separate respective first and second semiconductor chips and being of the lateral conductivity type, wherein said anode and cathode electrodes of each of said thyristors are on the same first surface of their said first and second chips respectively; said first surface of said first and second chips being optically sensitive, whereby said first and second chips can be switched to conduct current by illuminating said one surface; said solid state relay further comprising a light emitting diode arranged to illuminate said first surfaces upon its energization; a pair of a.c. terminals; said anode and cathode electrodes of said first and second thyristors connected to said pair of a.c. terminals and in anti-parallel relation with one another; a pair of control terminals insulated from said a.c. terminals and connected to said light emitting diode; and first and second control circuits connected to said gate circuits of said first and second thyristors respectively for clamping said first and second gate circuits respectively to prevent firing of said first and second thyristors when the voltage between said pair of a.c. terminals exceeds a given value and for clamping said first and second gate circuits in response to transient pulses having a dV/dt greater than a given value.

Claim 3

The solid state relay of claim 1, wherein said first and second control circuits include first and second control transistors respectively, each having an output circuit and a transistor control circuit operable to switch its respective control circuit between a conductive and a nonconductive condition; and first and second capacitor dividers; said first and second transistor output circuits connected between said gate circuit and said cathode electrode of its respective one of said first and second thyristors, whereby, when said first or second transistor output circuit is conductive, the respective one of said first or second thyristors cannot fire in response to illumination of its said first surface; said first and second capacitor dividers connected across said pair of a.c. terminals and having respective nodes between capacitors connected to said control circuit of the respective control transistor, whereby the voltage at said nodes renders its respective transistor conductive so long as the voltage between said pair of a.c. terminals exceeds a given value to prevent turn on of the respective one of said thyristors when the a.c. voltage exceeds a given window voltage, and whereby fast rising transient pulses turn on said transistors for their duration to prevent turn on of said thyristors by transient high dV/dt pulses.

Claim 4

A solid state relay comprising first and second thyristor chips connected in anti-parallel relation, and having respective anode and cathode electrodes and respective gate circuits; each of said first and second thyristors having one surface which is optically sensitive, whereby said first and second chips can be switched to conduct current by illuminating said one surface; said solid state relay further comprising a light emitting diode arranged to illuminate said one surface upon its energization; a pair of a.c. terminals; said first and second thyristors connected to said pair of a.c. terminals and in anti-parallel relation with one another; a pair of control terminals insulated from said a.c. terminals and connected to said light emitting diode; first and second control circuits connected to said gate circuits of said first and second thyristors respectively for clamping said first and second gate circuits respectively to prevent firing of said first and second thyristors when the voltage between said pair of a.c. terminals exceeds a given value and for clamping said first and second gate circuits in response to transient pulses having a dV/dt greater than a given value; said first and second control circuits including first and second control transistors respectively, each having an output circuit and a transistor control circuit operable to switch its respective control circuit between a conductive and a nonconductive condition; and first and second capacitor dividers; said first and second transistor output circuits connected between said gate circuit and said cathode electrode of its respective one of said first and second thyristors, whereby, when said first or second transistor output circuit is conductive, the respective one of said first or second thyristors cannot fire in response to illumination of its said first surface; said first and second capacitor dividers connected across said pair of a.c. terminals and having respective nodes between capacitors connected to said control circuit of the respective control transistor, whereby the voltage at said nodes renders its respective transistor conductive so long as the voltage between said a.c. terminals exceeds a given value to prevent turn on of the respective one of said thyristors when the a.c. voltage exceeds a given window voltage, and whereby fast rising transient pulses turn on said transistors for their duration to prevent turn on of said thyristors by transient high dV/dt pulses.

Claim 5

A solid state relay comprising first and second thyristor chips connected in anti-parallel relation, and having respective anode and cathode electrodes and respective gate circuits; each of said first and second thyristors having one surface which is optically sensitive, whereby said first and second chips can be switched to conduct current by illuminating said one surface; said solid state relay further comprising a light emitting diode arranged to illuminate said one surface upon its energization; a pair of a.c. terminals; said first and second thyristors connected to said pair of a.c. terminals and in anti-parallel relation with one another; a pair of control terminals insulated from said a.c. terminals and connected to said light emitting diode; first and second control circuits connected to said gate circuits of said first and second thyristors respectively for clamping said first and second gate circuits respectively to prevent firing of said first and second thyristors when the voltage between said pair of a.c. terminals exceeds a given value and for clamping said first and second gate circuits in response to transient pulses having a dV/dt greater than a given value; said first and second control circuits including first and second control transistors respectively, each having an output circuit and a transistor control circuit operable to switch its respective control circuit between a conductive and a nonconductive condition; and first and second capacitor dividers; said first and second transistor output circuits connected between said gate circuit and said cathode electrode of its respective one of said first and second thyristors, whereby, when said first or second transistor output circuit is conductive, the respective one of said first or second thyristors cannot fire in response to illumination of its said first surface; said first and second capacitor dividers connected across said pair of a.c. terminals and having respective nodes between capacitors connected to said control circuit of the respective control transistor, whereby the voltage at said nodes renders its respective transistor conductive so long as the voltage between said a.c. terminals exceeds a given value to prevent turn on of the respective one of said thyristors when the a.c. voltage exceeds a given window voltage, and whereby fast rising transient pulses turn on said transistors for their duration to prevent turn on of said thyristors by transient high dV/dt pulses.

Claim 6

The solid state relay of claim 2 or 3, wherein said first and second control circuits further include first and second zener diodes respectively connected from said nodes of said first and second capacitor dividers respectively to the cathode electrodes of said first and second thyristors respectively.

Claim 7

The solid state relay of claim 2 or 3, which further includes first and second resistors connected between said gate circuit of said first and second thyristors respectively to the cathode electrode of said first and second thyristors respectively.

Claim 8

The solid state relay of claim 4, which further includes first and second resistors connected between said gate circuit of said first and second thyristors respectively to the cathode electrode of said first and second thyristors respectively.

Claim 9

The solid state relay of claim 2 or 3, wherein said first and second transistors are metal oxide semiconductor field effect transistors and wherein said transistor control circuits include the gate circuit of said transistors.

Claim 10

The solid state relay of claim 4, wherein said first and second transistors are metal oxide semiconductor field effect transistors and wherein said transistor control circuits include the gate circuit of said transistors.

Claim 11

The solid state relay of claim 5, wherein said first and second transistors are metal oxide semiconductor field effect transistors and wherein said transistor control circuits include the gate circuit of said transistors.

Claim 12

The solid state relay of claim 6, wherein said first and second transistors are metal oxide semiconductor field effect transistors and wherein said transistor control circuits include the gate circuit of said transistors.

Claim 13

The solid state relay of claim 2 or 3, wherein said first and second capacitor dividers comprise first and second capacitors connected at said node.

Claim 14

The solid state relay of claim 4, wherein said first and second capacitor dividers comprise first and second capacitors connected at said node.

Claim 15

The solid state relay of claim 5, wherein said first and second capacitor dividers comprise first and second capacitors connected at said node.

Claim 16

The solid state relay of claim 6, wherein said first and second capacitor dividers comprise first and second capacitors connected at said node.

Claim 17

The solid state relay of claim 7, wherein said first and second capacitor dividers comprise first and second capacitors connected at said node.

Claim 18

The solid state relay of claim 15, wherein said second capacitor of each of said first and second capacitor dividers is the distributed capacitance of said first and second transistors respectively.

Claim 19

The solid state relay of claim 1, which further includes an electrically insulative but thermally conductive ceramic substrate for mounting said first and second chips and said light emitting diode; said first and second chips and said light emitting diode being fixed to the same surface of said substrate and spaced from one another; said optically sensitive surfaces of said first and second chips facing away from said substrate; said light emitting diode being in a position which enables illumination of said first and second chips by reflection of its light output from reflecting surfaces.

Claim 20

The solid state relay of claim 17, which includes first and second conductive strips on said substrate which extend to first and second output terminals disposed at the periphery of said substrate; and first and second continuous conductive wires; one end of said first and second conductive wires bonded to portions of said first and second conductive strips; the opposite ends of said first and second strips bonded to said cathode electrode of said first thyristor and said anode electrode of said second thyristor; and a generally central region of each of said strips being bonded to said anode electrode of said first thyristor and said cathode electrode of said second thyristor.

Claim 21

The solid state relay of claim 18, which further includes third and fourth conductive strips on said substrate; each of said third and fourth strips extending to third and fourth output terminals on the periphery of said substrate; said light emitting diode fixed to said third conductive strip and electrically connected to said fourth conductive strip whereby said diode is excited by application of an input voltage to said third and fourth terminals.

Claim 22

The solid state relay of claim 19, wherein said first, second, third and fourth terminals extend from the same side of said substrate.

Claim 23

The solid state relay of claim 19, wherein said first and third terminals extend from one side of said substrate and said second and fourth terminals extend from an opposite side of said substrate.

Claim 24

The solid state relay of claim 18 or 19, wherein said first and second control circuits include first and second control transistors respectively, each having an output circuit and a transistor control circuit operable to switch its respective control circuit between a conductive and a nonconductive condition; and first and second capacitor dividers respectively; said first and second transistor output circuits connected between said gate circuit and said cathode electrode of its respective one of said first and second thyristors, whereby, when said first or second transistor output circuit is conductive, the respective one of said first or second thyristors cannot fire in response to illumination of its said first surface; said first and second capacitor dividers connected across said pair of a.c. terminals and having respective nodes between capacitors connected to said control circuit of the respective control transistor, whereby the voltage at said nodes renders its respective transistor conductive so long as the voltage between said a.c. terminals exceeds a given value to prevent turn on of the respective one of said thyristors when the a.c. voltage exceeds a given window voltage, and whereby fast rising transient pulses turn on said transistors for their duration to prevent turn on of said thyristors by transient high dV/dt pulsees.

Claim 25

The relay of claim 2, wherein said first and second transistors respectively and said first and second voltage dividers respectively are integrally formed in said first and second chips.

Claim 26

The relay of claim 22, wherein said first and second transistors respectively and said first and second voltage dividers respectively are integrally formed in said first and second chips.