US4533877A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Telecommunication operational amplifier
Assignee: Nokia Bell Labs
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Filing: 1983-12-29
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Granted: 1985-08-06
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Expires: 2003-12-29
Abstract
Abstract A single stage high performance operational transconductance amplifier consists of a pair of p-channel load field effect transistors, a pair of n-channel type cascode field effect transistors, a pair of n-channel differential field effect transistors and an n-channel current source field effect transistor. This amplifier has improved performance in terms of noise and power supply rejection as compared to conventional CMOS amplifiers.
Inventors
- 👤 Chowdhury F. Rahim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:00
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F3/45188
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
441 words
An amplifier comprising: first and second load devices each having first and second terminals; third and fourth cascode switching devices each having a control terminal and first and second terminals; fifth and sixth differential switching devices each having a control terminal and first and second terminals; a current source coupled by a first terminal to the second terminals of the fifth and sixth differential switching devices; the control terminals of the differential pair of switching devices being coupled to first and second amplifier input terminals, respectively; the second terminals of the first and second load devices being coupled to the first terminals of the third and fourth cascode switching devices, respectively, and being adapted to be coupled to first and second amplifier output terminals, respectively; the second terminals of the third and fourth cascode switching devices being coupled to the first terminals of the fifth and sixth differential switching devices, respectively; each of the first, second, third, fourth, fifth, and sixth devices comprising a separate field effect transistor having a gate terminal corresponding to the control terminal, and having first and second terminals corresponding to the first and second terminals of the devices; the first and second transistors being n-channel or p-channel transistors and the third, fourth, fifth, and sixth transistors being of the opposite channel type of the first and second transistors; the first terminals of the first and second transistors being coupled together and being adapted to be connected to a first power supply; the gate terminals of the first and second transistors being coupled together and being adapted to be connected to a first reference potential; the gate terminals of the third and fourth transistors being coupled together and being adapted to be connected to a second reference potential; the current source comprising a seventh field effect transistor of opposite channel type as the first and second transistors, and having a gate terminal and first and second terminals; the first terminal of the seventh transistor being coupled to the second terminals of the fifth and sixth transistors; the second terminal of the seventh transistor being connectable to a second power supply; the gate terminal of the seventh transistor being connectable to a third reference potential; the first, second, and third reference potentials being generated by first, second, and third reference sources which each comprise field effect transistors; and wherein each of the first, second, and third reference sources comprises n-channel and p-channel transistors and the amplifier and all three reference sources are fabricated in a single semiconductor chip and each of the three reference sources and the amplifier are connectable to the same first and second power supplies.
Claim 2
Dependent Claim
441 words
An amplifier comprising: first and second load devices each having first and second terminals; third and fourth cascode switching devices each having a control terminal and first and second terminals; fifth and sixth differential switching devices each having a control terminal and first and second terminals; a current source coupled by a first terminal to the second terminals of the fifth and sixth differential switching devices; the control terminals of the differential pair of switching devices being coupled to first and second amplifier input terminals, respectively; the second terminals of the first and second load devices being coupled to the first terminals of the third and fourth cascode switching devices, respectively, and being adapted to be coupled to first and second amplifier output terminals, respectively; the second terminals of the third and fourth cascode switching devices being coupled to the first terminals of the fifth and sixth differential switching devices, respectively; each of the first, second, third, fourth, fifth, and sixth devices comprising a separate field effect transistor having a gate terminal corresponding to the control terminal, and having first and second terminals corresponding to the first and second terminals of the devices; the first and second transistors being n-channel or p-channel transistors and the third, fourth, fifth, and sixth transistors being of the opposite channel type of the first and second transistors; the first terminals of the first and second transistors being coupled together and being adapted to be connected to a first power supply; the gate terminals of the first and second transistors being coupled together and being adapted to be connected to a first reference potential; the gate terminals of the third and fourth transistors being coupled together and being adapted to be connected to a second reference potential; the current source comprising a seventh field effect transistor of opposite channel type as the first and second transistors, and having a gate terminal and first and second terminals; the first terminal of the seventh transistor being coupled to the second terminals of the fifth and sixth transistors; the second terminal of the seventh transistor being connectable to a second power supply; the gate terminal of the seventh transistor being connectable to a third reference potential; the first, second, and third reference potentials being generated by first, second, and third reference sources which each comprise field effect transistors; and wherein each of the first, second, and third reference sources comprises n-channel and p-channel transistors and the amplifier and all three reference sources are fabricated in a single semiconductor chip and each of the three reference sources and the amplifier are connectable to the same first and second power supplies.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-05 | 1989-02-04 | 1989-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-05 | 1993-02-04 | 1993-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-05 | 1997-02-04 | 1997-08-06 | $7700.00 | Window Closed / Lapsed |