Current limit technique for multiple-emitter vertical power transistor

Claim 1

Current limiting circuitry for a power transistor which includes a base, at least one collector and a plurality of emitters, comprising: first impedance means having a first terminal coupled to only a fraction of the number of said plurality of emitters and a second terminal coupled to a first source of supply voltage, said first impedance means having a value which is substantially different from any impedance in the remainder of said plurality of emitters; first means for turning said power transistor on and drawing a first current through said first impedance means which is related to the total current being conducted by said power transistor in a prescribed manner; and second means for monitoring the voltage across said first impedance means for limiting said first means when the voltage across said first impedance means reaches a certain level, said second means comprising a first transistor having base, emitter and collector terminals, said emitter being coupled to said second terminal of said first impedance means; a second transistor having base and collector terminals and the plurality of emitter terminals, each of said emitter terminals being coupled to said first terminal of said first impedance means, said first and second transistors having a base for coupling to a bias voltage which turns said first and second transistors and resulting in the generation of first and second currents respectively; and current mirror means coupled between a second source of supply voltage and said first and second transistors for generating a trigger when the voltage across said first impedance means reaches a certain level, said trigger being applied to said first means so as to limit current from said power transistor.