US4531224A
Expired / Lapsed
US
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Low signal-to-noise ratio symbol synchronizer
Assignee: Motorola Solutions Inc
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Filing: 1983-06-23
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Granted: 1985-07-23
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Expires: 2003-06-23
Abstract
Abstract A low SNR symbol synchronizer utilizes two quadrature channels and a delay and multiply technique to produce four product signals. Two of the product signals are same-channel products and two are cross-channel products. When combined and applied to a synchronizing apparatus such as a Costas loop, the signals provide improved performance at low SNR and avoid the need to know the carrier frequency when setting the delay.
Inventors
- 👤 Ronald D. McCallister
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:45
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027; H04L7/0274; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H04L27/0014; H04L2027/0044; H04L2027/0063; H04L2027/0067
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
152 words
Apparatus for use in a digital data receiver comprising: means for forming first and second quadrature signals from an input signal; means for forming delayed and undelayed versions of said first and second quadrature signals; means for multiplying said undelayed version of said first signal with said delayed version of said first signal to produce a first product; means for multiplying said undelayed version of said second signal with said delayed version of said second signal to produce a second product; means for multiplying said undelayed version of said second signal with said delayed version of said first signal to produce a third product; means for multiplying said undelayed version of said first signal with said delayed version of said second signal to produce a fourth product; and means for combining said first, second, third and fourth products to produce at least one signal indicative of a characteristic of said input signal.
Claim 2
Dependent Claim
152 words
Apparatus for use in a digital data receiver comprising: means for forming first and second quadrature signals from an input signal; means for forming delayed and undelayed versions of said first and second quadrature signals; means for multiplying said undelayed version of said first signal with said delayed version of said first signal to produce a first product; means for multiplying said undelayed version of said second signal with said delayed version of said second signal to produce a second product; means for multiplying said undelayed version of said second signal with said delayed version of said first signal to produce a third product; means for multiplying said undelayed version of said first signal with said delayed version of said second signal to produce a fourth product; and means for combining said first, second, third and fourth products to produce at least one signal indicative of a characteristic of said input signal.
Claim 3
Dependent Claim
58 words
An apparatus according to claim 1 wherein said means for combining further comprises: means for adding said first and second products to produce a sum; means for subtracting said third and fourth products to produce a difference; and means for utilizing said sum and difference to produce a signal synchronous with a timing rate of said input signal.
Claim 4
Dependent Claim
15 words
An apparatus according to claim 2 wherein said means for utilizing comprises: a Costas loop.
Claim 5
Dependent Claim
258 words
A low SNR symbol synchronizer comprising: means for producing an in-phase oscillator signal and a quad-phase oscillator signal; a first multiplier coupled to an input signal and to said in-phase oscillator signal and producing an I channel signal; a second multiplier coupled to said input signal and to said quad-phase oscillator signal and producing a Q channel signal; first and second low pass filters coupled to said first and second multipliers, respectively, for rejecting sum frequency components in said I and Q channel signals; first delay means coupled to an output of said first low pass filter for applying a predetermined delay to said I channel signal; second delay means coupled to an output of said second low pass filter for applying a delay identical to that applied by said first delay means to said Q channel signal; a third multiplier having inputs coupled to an output of said first low pass filter and an output of said first delay means; a fourth multiplier having inputs coupled to an output of said first delay means and an output of said first low pass filter; a fifth multiplier having inputs coupled to an output of said second delay means and an output of said first low pass filter; a sixth multiplier having inputs coupled to an output of said second low pass filter and an output of said second delay means; and synchronizing means coupled to outputs of said third, fourth, fifth and sixth multipliers for synchronizing a device to a data rate and phase of said input signal.
Claim 6
Dependent Claim
258 words
A low SNR symbol synchronizer comprising: means for producing an in-phase oscillator signal and a quad-phase oscillator signal; a first multiplier coupled to an input signal and to said in-phase oscillator signal and producing an I channel signal; a second multiplier coupled to said input signal and to said quad-phase oscillator signal and producing a Q channel signal; first and second low pass filters coupled to said first and second multipliers, respectively, for rejecting sum frequency components in said I and Q channel signals; first delay means coupled to an output of said first low pass filter for applying a predetermined delay to said I channel signal; second delay means coupled to an output of said second low pass filter for applying a delay identical to that applied by said first delay means to said Q channel signal; a third multiplier having inputs coupled to an output of said first low pass filter and an output of said first delay means; a fourth multiplier having inputs coupled to an output of said first delay means and an output of said first low pass filter; a fifth multiplier having inputs coupled to an output of said second delay means and an output of said first low pass filter; a sixth multiplier having inputs coupled to an output of said second low pass filter and an output of said second delay means; and synchronizing means coupled to outputs of said third, fourth, fifth and sixth multipliers for synchronizing a device to a data rate and phase of said input signal.
Claim 7
Dependent Claim
58 words
A low SNR symbol synchronizer according to claim 4 wherein said synchronizing means further comprises: means for subtracting an output of said fifth multiplier from an output of said fourth multiplier; means for adding an output of said third multiplier and an output of said sixth multiplier; and a Costas loop coupled to said adding and subtracting means.
Claim 8
Dependent Claim
26 words
A low SNR symbol synchronizer according to claim 4 wherein said first and second delay means each comprise: means for selectably applying one of several delays.
Claim 9
Independent Claim
146 words
A method of producing a signal indicative of a characteristic of an input signal comprising the steps of: forming first and second quadrature signals from said input signal; forming delayed and undelayed versions of said first and second quadrature signals; multiplying said delayed and undelayed versions of said first quadrature signal to produce a first product signal; multiplying said delayed and undelayed versions of said second quadrature signal to produce a second product signal; multiplying said delayed version of said first quadrature signal with said undelayed version of said second quadrature signal to produce a third product signal; multiplying said delayed version of said second quadrature signal with said undelayed version of said first quadrature signal to produce a fourth product signal; and combining said first, second, third and fourth product signals to produce at least one signal indicative of a charcteristic of said input signal.
Claim 10
Independent Claim
146 words
A method of producing a signal indicative of a characteristic of an input signal comprising the steps of: forming first and second quadrature signals from said input signal; forming delayed and undelayed versions of said first and second quadrature signals; multiplying said delayed and undelayed versions of said first quadrature signal to produce a first product signal; multiplying said delayed and undelayed versions of said second quadrature signal to produce a second product signal; multiplying said delayed version of said first quadrature signal with said undelayed version of said second quadrature signal to produce a third product signal; multiplying said delayed version of said second quadrature signal with said undelayed version of said first quadrature signal to produce a fourth product signal; and combining said first, second, third and fourth product signals to produce at least one signal indicative of a charcteristic of said input signal.
Claim 11
Dependent Claim
48 words
A method according to claim 7 wherein said step of combining said first, second, third and fourth product signals comprises the steps of: adding said first and second product signals to produce a sum signal; and subtracting said third and fourth product signals to produce a difference signal.
Claim 12
Dependent Claim
34 words
A method according to claim 8 further comprising the step of: applying said sum and difference signals to a Costas loop to produce a tone synchronized to a baud rate of said input signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-22 | 1989-01-21 | 1989-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-22 | 1993-01-21 | 1993-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-22 | 1997-01-21 | 1997-07-23 | $7700.00 | Window Closed / Lapsed |