Protective power foldback circuit for a power semiconductor

Claim 2

A protective power foldback circuit for a power semiconductor device which may otherwise be adversely affected by variations of load, supply voltage, and drive power thereto, comprising: means for generating a reference voltage; means for sampling the supply voltage applied to the power semiconductor device; means for comparing said reference voltage and said sampled supply voltage and generating a foldback control signal in response to an excess of applied supply voltage; and means for reducing the drive power applied to the power semiconductor device by a predetermined amount greater than that produced by said excess of applied supply voltage in response to said foldback control signal.

Claim 3

A protective power foldback circuit in accordance with claim 1, wherein said power semiconductor device is a transistor.

Claim 4

A protective power foldback circuit in accordance with claim 1, wherein said reference voltage is developed across a zener diode.

Claim 5

A protective power foldback circuit in accordance with claim 1, wherein said supply voltage applied to said power semiconductor device is sampled via a resistive voltage divider.

Claim 6

A protective power foldback circuit in accordance with claim 1, wherein a transistor comparator is used to compare said reference voltage, applied at one terminal, and said sampled supply voltage, applied at a second terminal, to generate a foldback control signal at a third terminal.

Claim 7

A protective power foldback circuit in accordance with claim 1, wherein said reducing means is a driver stage with variable output power responsive to supply voltage applied to said previous active stage.

Claim 8

A protective power foldback circuit for a power semiconductor device, incorporated in an output power control loop generating a control voltage, which may otherwise be adversely affected by variations of load, supply voltage, and drive power thereto, comprising: means for generating a reference voltage; means for sampling the supply voltage applied to the power semiconductor device; means for sampling the control voltage; means for summing said sampled supply voltage and said sampled control voltage in predetermined proportions; means for comparing said summed output to said reference voltage and generating a foldback control signal in response to an excess of applied supply voltage; and means for reducing the drive power applied to the power semiconductor device by a predetermined amount greater than that produced by said excess of applied supply voltage in response to said foldback control signal input to the power control loop.

Claim 9

A protective power foldback circuit for a power semiconductor device, incorporated in an output power control loop generating a control voltage, which may otherwise be adversely affected by variations of load, supply voltage, and drive power thereto, comprising: means for generating a reference voltage; means for sampling the supply voltage applied to the power semiconductor device; means for sampling the control voltage; means for summing said sampled supply voltage and said sampled control voltage in predetermined proportions; means for comparing said summed output to said reference voltage and generating a foldback control signal in response to an excess of applied supply voltage; and means for reducing the drive power applied to the power semiconductor device by a predetermined amount greater than that produced by said excess of applied supply voltage in response to said foldback control signal input to the power control loop.

Claim 10

A protective power foldback circuit in accordance with claim 7, wherein said power semiconductor device is a transistor.

Claim 11

A protective power foldback circuit in accordance with claim 7, wherein said reference voltage is developed across a zener diode.

Claim 12

A protective power foldback circuit in accordance with claim 7, wherein said supply voltage and said control voltage are sampled in predetermined proportions and summed in a resistive network.

Claim 13

A protective power foldback circuit in accordance with claim 7, wherein a transistor comparator is used to compare said reference voltage, applied at one terminal, and said summed output, applied at a second terminal, to generate a foldback control signal at a third terminal.

Claim 16

A method of protective power foldback in accordance with claim 12 wherein comparing said reference voltage to said sampled supply voltage is further comprised of the steps: applying said reference voltage to a first terminal of a transistor comparator; applying said sampled supply voltage to a second terminal of a transistor comparator; and generating a foldback control signal at a third terminal of a transistor comparator.

Claim 19

A method of protective power foldback in accordance with claim 14, wherein comparing said reference voltage to said summed output is further comprised of the steps: applying said reference voltage to a first terminal of a transistor comparator; applying said summed output to a second terminal of a transistor comparator; and generating a foldback control signal at a third terminal of a transistor comparator.