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US4529946A Expired / Lapsed US ⏱️ 0.0 years remaining

Differential amplifier circuit

Assignee: Toshiba Corp
•
Filing: 1983-09-28
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Granted: 1985-07-16
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Expires: 2003-09-28
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Abstract

Abstract A differential amplifier circuit producing sufficient output current with a broad linear working range, which includes first and second transistors coupled at their emitters in differential amplifier configuration, an input circuit means connected between the bases of the first and second transistors, third and fourth transistors connected to the collectors of the first and second transistors constituting collector loads of the first and second transistors respectively, first resistor inserted between the bases of the third and fourth transistors, second and third resistors respectively inserted between the base and collector of each of the third and fourth transistors, and an output circuit means connected to the third and fourth transistors.

Inventors

  • 👤 Hiromi Kusakabe

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 16:43
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3211

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 99 words
A differential amplifier circuit comprising: first and second transistors coupled at their emitters with each other in differential amplifier configuration; input circuit means connected between the bases of said first and second transistors; third and fourth transistors connected to the collectors of said first and second transistors constituting collector loads of said first and second transistors respectively; first resistor inserted between the bases of said third and fourth transistors; second and third resistors respectively inserted between the base and collector of each of said third and fourth transistors; and output circuit means connected to said third and fourth transistors.
Claim 2
Dependent Claim 99 words
A differential amplifier circuit comprising: first and second transistors coupled at their emitters with each other in differential amplifier configuration; input circuit means connected between the bases of said first and second transistors; third and fourth transistors connected to the collectors of said first and second transistors constituting collector loads of said first and second transistors respectively; first resistor inserted between the bases of said third and fourth transistors; second and third resistors respectively inserted between the base and collector of each of said third and fourth transistors; and output circuit means connected to said third and fourth transistors.
Claim 3
Dependent Claim 18 words
A differential amplifier circuit according to claim 1, wherein said second and third resistors have equal resistance value.
Claim 4
Dependent Claim 46 words
A differential amplifier circuit according to claim 1, wherein said output circuit means is comprised of fifth and sixth transistors having their bases connected to said third and fourth transistors to constitute first and second current mirror circuits together with said third and fourth transistors respectively.
Claim 5
Dependent Claim 35 words
A differential amplifier circuit according to claim 3, further comprising: fourth and fifth resistors respectively connected to the bases of said fifth and sixth transistors and to the collector of the third and fourth transistor.
Claim 6
Dependent Claim 20 words
A differential amplifier circuit according to claim 4, wherein said second to fifth resistors each has the same resistance value.

References Cited (Backward Citations)

JPS4827664A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-07-15 1989-01-14 1989-07-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-07-15 1993-01-14 1993-07-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-07-15 1997-01-14 1997-07-16 $7700.00 Window Closed / Lapsed

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