Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
301 words
In a house system for the transmission of information messages which are encoded in the form of digital signals, wherein a house code specific to the house system is selected adapted for the testing of each information bit, including a central station and a series of substations at which the information messages of the central stations are selectively transmittable through the electrical power supply as a transmission path which is utilized by further similar systems, wherein each substation terminates further information evaluation on the basis of an information bit recognized as erroneous, and wherein each information message includes a selectable subsequence of digital signals specific to the house system occurring at other than the end of the total sequence of digital signals representing the information message, the improvement comprising: (a) said central station emitting an electrical operating signal during the duration of each information message emitted thereby; (b) a monitoring unit for receiving the operation signal; (c) said monitoring unit containing (aa) a receiving component for the information message connected to the transmission path; (bb) a memory having the subsequence of digital signals having the house code specific to the house system stored therein; (cc) a comparator means, coupled to said receiving component and said memory, within which there is analyzed the information message for the occurrence of the sequence of digital signals specific to the house system; (dd) and a transmitting component connected at its output to the transmission path and coupled at its input to said comparator means for emitting a signal on the transmission path effectuating a code alteration in the information message when in an incoming information message on the transmission path there occurs a subsequence of digital signals specific to the house system without the concurrent presence of the operation signal emitted by said central station.
Claim 2
Dependent Claim
301 words
In a house system for the transmission of information messages which are encoded in the form of digital signals, wherein a house code specific to the house system is selected adapted for the testing of each information bit, including a central station and a series of substations at which the information messages of the central stations are selectively transmittable through the electrical power supply as a transmission path which is utilized by further similar systems, wherein each substation terminates further information evaluation on the basis of an information bit recognized as erroneous, and wherein each information message includes a selectable subsequence of digital signals specific to the house system occurring at other than the end of the total sequence of digital signals representing the information message, the improvement comprising: (a) said central station emitting an electrical operating signal during the duration of each information message emitted thereby; (b) a monitoring unit for receiving the operation signal; (c) said monitoring unit containing (aa) a receiving component for the information message connected to the transmission path; (bb) a memory having the subsequence of digital signals having the house code specific to the house system stored therein; (cc) a comparator means, coupled to said receiving component and said memory, within which there is analyzed the information message for the occurrence of the sequence of digital signals specific to the house system; (dd) and a transmitting component connected at its output to the transmission path and coupled at its input to said comparator means for emitting a signal on the transmission path effectuating a code alteration in the information message when in an incoming information message on the transmission path there occurs a subsequence of digital signals specific to the house system without the concurrent presence of the operation signal emitted by said central station.
Claim 3
Dependent Claim
20 words
System as claimed in claim 1, wherein the information message is transmitted as a digital signal modulating a carrier frequency.
Claim 4
Dependent Claim
39 words
System as claimed in claim 1, wherein a biphase code is selected as the code adapted for the testing of each information bit, in which there is repeated a logic value in inverted form associated with an information bit.
Claim 5
Dependent Claim
21 words
System as claimed in claim 3, wherein a digital signal forming a logic value is formed as a sinusoidal wave train.
Claim 6
Dependent Claim
26 words
System as claimed in claim 1, wherein the subsequence of digital signals specific to the house system is arranged at the beginning of the information message.
Claim 7
Dependent Claim
22 words
System as claimed in claim 2, wherein the receiving component includes a selective receiver correlated to the carrier frequency, and a demodulator.
Claim 8
Dependent Claim
29 words
System as claimed in claim 1, wherein each information bit of the information message is emitted in the region of a zero crossing passage of the power supply voltage.
Claim 9
Dependent Claim
65 words
System as claimed in claim 1, wherein the comparator means includes an electronic message memory for at least the subsequence of digital signals specific to the house system, having an input connected with the output of the demodulator, and wherein the output of the demodulator is connected with an input of an electronic comparator, the memory being connected to the second input of the comparator.
Claim 10
Dependent Claim
14 words
System as claimed in claim 8, wherein said message memory comprises a shift register.
Claim 11
Dependent Claim
78 words
System as claimed in claim 8, wherein the output signal of the comparator and the inverted operating signal are logically conjunctively interconnected in an AND gate in operative connection with the trigger input of the transmitting component which subsequent to the trigger at the timepoint of the occurrence of the subsequent information bit emits a sinusoidal wave train in the carrier frequency whose duration corresponds to at least the duration of an information bit in the biphase code.
Claim 12
Dependent Claim
31 words
System as claimed in claim 3, wherein a biphase decoder is connected to the output of the receiving component, whose output signal is transmitted to the input of the message memory.
Claim 13
Dependent Claim
23 words
System as claimed in claim 11, wherein said biphase decoder is formed of a two stage shift register consisting of two flip flops.
Claim 14
Dependent Claim
138 words
System as claimed in claim 11 including a biphase code tester having an input in operative connection with the biphase decoder and an output providing a resetting signal for a message counter coupled to the output of said biphase code tester upon the occurrence of a code alteration in the information message, wherein the message counter counts the input of a subsequence of digital signals specific to the applicable system, an interrogating unit coupled to the output of the message counter, said interrogating unit having an output signal active after the complete input of the subsequence of digital signals specific to the house system without code alteration, and wherein the output signal of the interrogating element in conjunction with the output signal of the comparator and the inverted operating signal are logically conjunctively interconnected in an AND gate.
Claim 15
Dependent Claim
47 words
System as claimed in claim 13, wherein a monostable flip flop is connected to the output of the AND gate wherein the unstable condition of the flip flop subsequent to the setting continues at least to the completion of the subsequent information bit in the information message.
Claim 16
Dependent Claim
68 words
A system as claimed in claim 7, wherein the output signal of the monostable flip flop is logically conjunctively interengaged in a further AND gate with a signal which is exclusively active in the region of the zero crossing passage of the power supply alternating current for the duration of an information bit, whereby the output signal of the further AND gate places the transmitting component into operation.
Claim 17
Dependent Claim
39 words
System as claimed in claim 2, wherein a biphase code is selected as the code adapted for the testing of each information bit, in which there is repeated a logic value in inverted form associated with an information bit.
Claim 18
Dependent Claim
78 words
System as claimed in claim 9, wherein the output signal of the comparator and the inverted operating signal are logically conjunctively interconnected in an AND gate in operative connection with the trigger input of the transmitting component which subsequent to the triggering at the timepoint of the occurrence of the subsequent information bit emits a sinusoidal wave train in the carrier frequency whose duration corresponds to at least the duration of an information bit in the biphase code.
Claim 19
Dependent Claim
138 words
System as claimed in claim 12, including a biphase code tester having an input in operative connection with the biphase decoder and an output providing a resetting signal for a message counter coupled to the output of said biphase code tester upon the occurrence of a code alteration in the information message, wherein the message counter counts the input of a subsequence of digital signals specific to the applicable system, an interrogating unit coupled to the output of the message counter, said interrogating unit having an output signal active after the complete input of the subsequence of digital signals specific to the house system without code alteration, and wherein the output signal of the interrogating element in conjunction with the output signal of the comparator and the inverted operating signal are logically conjunctively interconnected in an AND gate.
Claim 20
Dependent Claim
68 words
A system as claimed in claim 14, wherein the output signal of the monostable flip flop is logically conjunctively interengaged in a further AND gate with a signal which is exclusively active in the region of the zero crossing passage of the power supply alternating current for the duration of an information bit, whereby the output signal of the further AND gate places the transmitting component into operation.