Wafer scale integrated circuit memories

Claim 2

An integrated circuit for use in concatenating first and second memory blocks, comprising: a plural location data store; a through-passing data path for receiving a succession of data characters from said first memory block and for passing a succession of data characters to said second memory block; a through-passing control path for receiving a succession of control characters from said first memory block and for passing a succession of control characters to said second memory block; a through-passing address path for receiving a succession of key word address characters from said first memory block and for passing said succession of key word address characters to said second memory block; a control decoder for monitoring the contents of said control path and for providing, in response to the received succession of control characters, a control signal output; a data comparator for receiving said succession of key word address characters and operable, in response to said control signal output from said decoder, to compare said succession of key word address characters with the contents of a selectable succession of locations in said store and to detect a selectable one out of a plurality of magnitude relationships between said key word address characters and said contents of said succession of locations in said store and provide an indication of the magnitude relationship as an output signal; and, a data switch responding to said control signal from said decoder and said magnitude relationship output signal from said data comparator to switch said data between said data path and said store, along said data path or within said store.

Claim 3

A memory block according to claim 1 wherein said switch is operable to perform a range of data steering operations including: retention of data in said store while coupling said succession of data characters received from said first memory block as said succession of data characters passed to said second memory block; the storage in said store of said succession of data characters received from said first memory block while providing as said succession of data characters passed to said second memory block the previous contents of said store; the retention of data in said store, while ignoring said succession of characters received from said first memory block, and while providing a replica of data in said store as said succession of characters passed to said second memory block; and, the coupling of said succession of data characters received from said first memory block as said succession of data characters passed to said second memory block while storing said succession of received data characters and while discarding the previous contents of said store.

Claim 4

A memory block according to claim 2 wherein said control decoder comprises a control character modifier operable in response to the receipt of one or more predetermined control characters from said first memory block and in response to the output of said data comparator, to provide a modified succession of control characters for coupling to said memory block in said control path, but otherwise to provide as said succession of control characters for coupling to said second memory block in said control path the same succession of control characters as said control decoder receives from said first memory block.

Claim 5

A memory block according to claim 3 wherein said plurality of selectable magnitude relationships includes said key word address characters being equal to the stored data word selected from among the data in said store, said key word address character being less than or equal to said stored data word, said key word address character being less than said stored data word, said key word address character being equal to or greater than said stored data word, and said keyword address character being greater than said stored data word.

Claim 6

A memory block according to claim 4 wherein said store is a serial-in serial-out shift register and wherein said retention of data in said store consists in coupling the output of said shift register to the input of said shift register for data to circulate therethrough.

Claim 7

A memory block according to claim 5 wherein said data path comprises a unit delay latch between said first memory block and said data switch, said key word address path comprises a second unit delay latch between said first memory block and said comparator, and said control path comprises a third unit delay latch between said first memory block and said decoder, and wherein said register and said first, second, and third delay latches are all in receipt of a common clocking signal, said latches in response thereto transferring and maintaining at their respective output the logical state of their respective inputs and said shift register responding thereto by shifting its contents by one location between said input of said shift register and said output of said shift register.

Claim 8

A memory block according to claim 6 wherein said control decoder comprises a control state machine operable to recognise a first control character indicative of the selection of a generic command type, and thereafter operable to recognise one or more subsequent control characters operative to select one out of a plurality of manners of execution of said generic command type, said state machine inhibiting said output of said control decoder until after said recognition of said one or more subsequent control characters.

Claim 9

A memory block according to claim 7 wherein said data characters received from said first memory block are provided in the form of a stream of serial binary digits, said data characters passed to said second memory block are provided in the form of a stream of serial binary digits, said address words are received from said first memory block as a serial stream of binary digits, and passed to said second memory block as a serial stream of binary digits, and said control characters are received from said first memory block as a serial succession of plural parallel binary digit words and passed to said second memory block as a serial succession of plural, parallel binary digit words.

Claim 10

An integrated circuit for use in concatenating first and second memory blocks, comprising: a plural location data store; a through-passing data path for receiving a succession of data characters from said first memory block and for passing a succession of data characters to said second memory block; a through-passing control path for receiving a succession of control characters from said first memory block and for passing a succession of control characters to said second memory block; a through-passing address path for receiving a succession of key word address characters from said first memory block and for passing said succession of key work address characters to said second memory block; a control decoder for monitoring the contents of said control path and for providing, in response to the received succession of control characters, a control signal output; a data comparator for receiving said succession of key word address characters and operable, in response to said control signal output from said decoder, to compare said succession of key word address characters with the contents of a selectable succession of locations in said store and to detect a selectable one out of a plurality of mangitude relationships between said key word address characters and said contents of said succession of locations in said store and provide an indication of the magnitude relationship as an output signal; and, a data switch responding to said control signal from said decoder and said magnitude relationship output signal from said data comparator to switch said data between said data path and said store, along said data path or within said store; a backward data output line for supplying the contents of said store to the backward data input line in said first memory block, as a succession of backward data output characters; and, a backward data input line for supplying a serial succession of backward data input characters received from the backward data output line of said second memory block to said data switch.

Claim 11

An integrated circuit for use in concatenating first and second memory blocks, comprising: a plural location data store; a through-passing data path for receiving a succession of data characters from said first memory block and for passing a succession of data characters to said second memory block; a through-passing control path for receiving a succession of control characters from said first memory block and for passing a succession of control characters to said second memory block; a through-passing address path for receiving a succession of key word address characters from said first memory block and for passing said succession of key work address characters to said second memory block; a control decoder for monitoring the contents of said control path and for providing, in response to the received succession of control characters, a control signal output; a data comparator for receiving said succession of key word address characters and operable, in response to said control signal output from said decoder, to compare said succession of key word address characters with the contents of a selectable succession of locations in said store and to detect a selectable one out of a plurality of mangitude relationships between said key word address characters and said contents of said succession of locations in said store and provide an indication of the magnitude relationship as an output signal; and, a data switch responding to said control signal from said decoder and said magnitude relationship output signal from said data comparator to switch said data between said data path and said store, along said data path or within said store; a backward data output line for supplying the contents of said store to the backward data input line in said first memory block, as a succession of backward data output characters; and, a backward data input line for supplying a serial succession of backward data input characters received from the backward data output line of said second memory block to said data switch.

Claim 12

A memory block according to claim 9 wherein said switch is operable to perform a range of data steering operations including: retention of data in said store while coupling said succession of data characters received from said first memory block as said succession of data characters passed to said second memory block; the storage in said store of said succession of data characters received from said first memory block while providing as said succession of data characters passed to said second memory block the previous contents of said store; the retention of data in said store, while ignoring said succession of characters received from said first memory block, and while providing a replica of data in said store as said succession of characters passed to said second memory block; and, the coupling of said backward data input characters on said backward data input line for storing in said store while coupling said serial succession of data characters received from said first memory block as said serial succession of data characters to said second memory block and discarding those characters previously stored in said store.

Claim 13

A memory block according to claim 10 wherein said control decoder comprises a control character modifier operable in response to the receipt of one or more predetermined control characters from said first memory block and in response to the output of said data comparator, to provide a modified succession of control characters, for coupling to said memory block in said control path, but otherwise to provide as said succession of control characters for coupling to said second memory block in said control path the same succession of control characters as said control decoder receives from said first memory block.

Claim 14

A memory block according to claim 11 wherein said plurality of selectable magnitude relationships includes; said key word address character being equal to the stored data word selected from among the data in said store, said key word address character being less than or equal to said stored data word, said key word address character being less than said stored data word, said key word address character being equal to or greater than said stored data word, and said key word address character being greater than said stored data word.

Claim 15

A memory block according to claim 12 wherein said store is a serial-in serial-out shift register wherein said retention of data in said store consists in coupling the output of said shift register to the input of said shift register for data to circulate therethrough, and wherein said backward data out line has thereon a representation of the data character stored in the penultimate position of said shift register.

Claim 16

A memory block according to claim 13 wherein said data path comprises a unit delay latch between said first memory block and said data switch, said key word address path comprises a second unit delay latch between said fist memory block and said comparator, and said control path comprises a third delay latch between said first memory block and said decoder and wherein said shift register and said first, second, and third delay latches are all in receipt of common clocking signals, said latches in response thereto transferring and maintaining at their respective outputs the logical state of their respective inputs and said shift register responding thereto by shifting its contents by one location between said input of said shift register and said output of said shift register.

Claim 17

A memory block according to claim 14 wherein said control decoder comprises a control state machine operable to recognise a first control character indicative of the selection of a generic command type and is thereafter operable to recognise one or more subsequent control characters operative to select one out of a plurality of manners of execution of said generic command type, said state machine inhibiting said output of said control decoder until after said recognition of said one or more subsequent control characters.

Claim 18

A memory block according to claim 15 wherein said data characters received from said first memory block are provided in the form of a stream serial binary digits, said data characters passed to said second memory block are provided in the form of serial binary digits, said key word address words are received from said first memory block as a serial stream of binary digits and passed to said second memory block as a serial stream of binary digits, and said control characters are received from said first memory block as a serial succession of plural parallel binary digit words and passed to said second memory block as a serial succession of plural, parallel binary digit words.