US4528553A
Expired / Lapsed
US
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Event detection apparatus
Assignee: ConocoPhillips Co
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Filing: 1983-08-16
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Granted: 1985-07-09
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Expires: 2003-08-16
Abstract
Abstract Circuitry for qualifying a series of randomly occurring alarm events to avoid erroneous indications. Alarm events occurring in a surveillance system or the like are counted over a selected time interval, and final alarm output is effected only if a selected 1+n number of events has been counted within the interval. Both the repetitive time intervals and the event number are variable in accordance with the exigencies of the alarm application.
Inventors
- 👤 Ray D. Hastings
- 👤 Ernest W. Boyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:49
CPC Classifications
G; G08; G08B; G08B29/00; G08B29/18; G08B29/185
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
148 words
Apparatus for developing an event and time variable electrical signal alarm indication, comprising: means responsive to a selected surveillance condition to produce one or more random event signals; first counter means receiving said event signals at the input and producing an event count output upon receiving a selected number 1+n of said event signals; clock means outputting time reference pulses; flip flop means energized by the first one of said event signals to produce a set output; gate means receiving time reference pulses and enabled by said set output to output said time reference pulses; second counter means counting said gated time reference pulses and producing an enabling pulse for a selected duration; AND gate means enabled by said selected duration enabling pulse from said second counter means to output any event count output from said first counter means; and alarm means responsive to said event count output.
Claim 2
Dependent Claim
148 words
Apparatus for developing an event and time variable electrical signal alarm indication, comprising: means responsive to a selected surveillance condition to produce one or more random event signals; first counter means receiving said event signals at the input and producing an event count output upon receiving a selected number 1+n of said event signals; clock means outputting time reference pulses; flip flop means energized by the first one of said event signals to produce a set output; gate means receiving time reference pulses and enabled by said set output to output said time reference pulses; second counter means counting said gated time reference pulses and producing an enabling pulse for a selected duration; AND gate means enabled by said selected duration enabling pulse from said second counter means to output any event count output from said first counter means; and alarm means responsive to said event count output.
Claim 3
Dependent Claim
51 words
Apparatus as set forth in claim 1 wherein said first counter means comprises: decade counter means receiving input of said event signals and providing a pulse output after count of 1+n event signals; and second flip flop means receiving set input of said pulse output to provide said event count output.
Claim 4
Dependent Claim
74 words
Apparatus as set forth in claim 1 wherein said second counter means comprises: binary counter means receiving said gated time reference pulses and providing a divided count output; up/down counter means actuated by said divided count output and generating a carry output of selected duration; and second AND gate means enabled by said flip flop means set output to conduct said carry output as said selected duration enabling pulse to said AND gate means.
Claim 5
Dependent Claim
74 words
Apparatus as set forth in claim 2 wherein said second counter means comprises: binary counter means receiving said gated time reference pulses and providing a divided count output; up/down counter means actuated by said divided count output and generating a carry output of selected duration; and second AND gate means enabled by said flip flop means set output to conduct said carry output as said selected duration enabling pulse to said AND gate means.
Claim 6
Dependent Claim
49 words
Apparatus as set forth in claim 4 which is further characterized to include: reset means providing a reset pulse to each of said flip flop means, decade counter means, second flip flop means, binary counter means and up/down counter means upon cessation of enablement of said AND gate means.
Claim 7
Dependent Claim
36 words
Apparatus as set forth in claim 4 wherein said alarm means comprises: transistor means rendered conductive in response to said event count output; and relay means actuated by said transistor means conduction to provide alarm indication.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-08 | 1989-01-07 | 1989-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-08 | 1993-01-07 | 1993-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-08 | 1997-01-07 | 1997-07-09 | $7700.00 | Window Closed / Lapsed |