Hiline interference eliminator

Claim 2

Means for substantially eliminating from a two conductor signal channel an undesired induced signal in a differential mode, wherein the undesired signal appears on the two conductors in a common mode signal component and in a differential mode signal component, said means comprising means for coupling from said two conductors a common mode signal component of the undesired signal, means for coupling from said two conductors a differential mode signal component of the undesired signal, correlating means for correlating said differential mode signal component with said common mode signal component to produce a correlation signal, means responsive to said correlation signal and to said common mode signal component for producing a correcting signal which when coupled to one of said conductors reduces said correlation signal substantially to zero.

Claim 3

The combination claimed in claim 1 wherein said correlating means includes, means for producing an in-phase correlation signal component, and means for producing a quadrature phase correlation signal component, said two correlation signal components being phased relative to the undesired signal on said conductors.

Claim 4

The combination claimed in claim 2 wherein said means for producing a correcting signal includes means responsive to said in-phase correlation signal component and to said common mode signal component for producing a first correcting signal component for substantially eliminating from the two conductors the in-phase component of the undesired differential mode signal, and means responsive to the quadrature phase correlation signal component and to said common mode signal component for producing a second correcting signal component for substantially eliminating from said two conductors the quadrature phase component of the undesired differential mode signal.

Claim 5

The combination claimed in claim 3 wherein said means for producing a correcting signal includes, a first correcting resistor and a first correcting capacitor each having one end connected to a first one of said conductors of the signal channel, a second correcting resistor and a second correcting capacitor each having one end connected to the second one of said conductors of the signal channel, means for coupling said first correcting signal component to the other end of said first correcting resistor, means for coupling said second correcting signal component to said first correcting capacitor, and means for connecting the other ends of said second correcting resistor and second correcting capacitor to ground.

Claim 6

The combination claimed in claim 4 wherein said two conductors are the hi and lo conductors of a signal channel, and wherein said first conductor is the hi conductor of the signal channel.

Claim 7

The combination claimed in claim 1 wherein said correlating means includes, signal multiplying means for multiplying said common mode and differential mode signal components of the undesired signal, and signal averaging means for averaging the output signal of said signal multiplying means.

Claim 8

The combination claimed in claim 6 wherein said correlating means includes, means for shifting by 90° the phase of one of said common mode or differential mode signal components, means for coupling to said signal multiplying means first the unshifted and then the shifted signal component of said one of the common mode or differential mode signal components, and means for coupling the other one of the common mode or differential mode or differential mode signal components to the signal multiplying means when said shifted and unshifted components of said one signal component are coupled to the signal multiplying means.

Claim 9

The combination claimed in claim 4 wherein the means for producing said correcting signals include means responsive to said correlating signal for producing a count that is a function of the correlating signal when the correcting signal is zero, means for multiplying said count and said common mode signal component to obtain said correcting signal, said means for producing said count operating to maintain a count which when multiplied by said common mode signal reduces said correlating signal substantially to zero.

Claim 10

The combination claimed in claim 8 wherein said means for multiplying said count and said common mode signal is a multiplying digital to analog converter that produces an output signal that may vary in both directions from a zero output.

Claim 11

The combination claimed in claim 9 wherein said means for producing a count includes, an up/down counter, and means responsive to the sign of the correlating signal to command the counter to count up or down depending on the sign of the correlating signal.

Claim 14

The method claimed in claim 11 wherein the step of producing a correlating signal includes, producing an in-phase correlation signal component, and producing a quadrature phase correlation signal component, said two correlation signal components being phased relative to the undesired signal on said conductors.

Claim 15

The method claimed in claim 12 wherein the step of producing a correcting signal includes operating on each of said two correlation signal components with said common mode signal component to produce respective correcting signals which when connected to one of said conductors reduces said correlation signal components substantially to zero.

Claim 16

The method claimed in claim 13 wherein the step of producing correcting signals includes, producing respective counts that are functions of the two correlating signals when the correcting signals are zero, multiplying each of said counts with said common mode signal component to obtain respective correcting signals, and maintaining respective counts that cause said correlating signals to go substantially to zero.

Claim 17

The method claimed in claim 14 wherein the step of producing respective counts includes, counting in one direction when the respective correlating signal has one sign and counting in the opposite direction when the respective correlating signal has the opposite sign.

Claim 18

The method claimed in claim 15 wherein the steps of producing an in-phase correlation signal component and a quadrature phase signal component includes, alternately producing the in-phase and quadrature phase correlation signal components.

Claim 19

Circuitry for substantially eliminating from a two wire seismic signal channel an undesired induced hiline interference signal in a differential mode, wherein the undesired hiline interference signal also is present on the lines in a common mode component, said circuitry comprising a common mode amplifier coupled to the two wires of the seismic channel for producing a hiline common mode signal having substantially no hiline differential mode component therein, a differential mode amplifier coupled to the two wires of the seismic channel for producing a hiline differential mode signal having substantially no hiline common mode component therein, phase shifting means responsive to said hiline common mode signal for producing a quadrature phase hiline common mode signal, multiplexing means for producing a multiplexed signal comprised of said hiline common mode signal that occurs during a first one of alternately occuring time periods followed by said quadrature phase hiline common mode signal during the other one of said alternately occurring time periods, signal correlation means responsive to said multiplexed signal and to said hiline differential mode signal for correlating the hiline common mode signal and the quadrature phase hiline common mode signal with said hiline differential mode signal and producing respective alternately ocurring first and second correlating signals in response thereto, means responsive to said correlating signals for producing respective up/down count command signals that have different characteristics when the respective correlating signal has different signs, means responsive to said correlating signals for producing corresponding clock signals whose frequencies are functions of the magnitudes of the respective correlating signal, without regard to the sign of the respective correlating signal, first counter means responsive to a first one of said up/down command signals and to a first one of said clock signals for producing a first count that is a function of the magnitude of said first correlating signal without any correction applied to said seismic channel, said first up/down command signal and the first correlating signal being associated with said hiline common mode signal, second counter means responsive to the second one of said up/down command signals and to said second correlating signal for producing a second count that is a function of the magnitude of the second correlating signal without any correction applied to said seismic channel, a first multiplying means for multiplying said first count with said hiline common mode signal to produce a first analog correcting signal, a second multiplying means for multiplying said second count with said hiline common mode signal to produce a second analog signal, resistor means for coupling said first correcting signal to a hi one of the two wires of the seismic channel, capacitor means for coupling said second correcting signal to said hi one of the two wires of the seismic channel, substantially identical resistor and capacitor means connected between the lo one of said two wires and ground, said first and second multiplying means operating to produce respective correcting signals that reduce said first and second correlating signals substantially to zero, said first and second counter means retaining respective counts that cause said correcting signals to reduce the correlation between said hiline common mode signal and said hiline differential mode signal to zero and to reduce the correlation between the quadrature phase hiline common mode signal and the hiline differential mode signal to zero.

Claim 20

Circuitry for substantially eliminating from a two wire seismic signal channel an undesired induced hiline interference signal in a differential mode, wherein the undesired hiline interference signal also is present on the lines in a common mode component, said circuitry comprising a common mode amplifier coupled to the two wires of the seismic channel for producing a hiline common mode signal having substantially no hiline differential mode component therein, a differential mode amplifier coupled to the two wires of the seismic channel for producing a hiline differential mode signal having substantially no hiline common mode component therein, phase shifting means responsive to said hiline common mode signal for producing a quadrature phase hiline common mode signal, multiplexing means for producing a multiplexed signal comprised of said hiline common mode signal that occurs during a first one of alternately occuring time periods followed by said quadrature phase hiline common mode signal during the other one of said alternately occurring time periods, signal correlation means responsive to said multiplexed signal and to said hiline differential mode signal for correlating the hiline common mode signal and the quadrature phase hiline common mode signal with said hiline differential mode signal and producing respective alternately ocurring first and second correlating signals in response thereto, means responsive to said correlating signals for producing respective up/down count command signals that have different characteristics when the respective correlating signal has different signs, means responsive to said correlating signals for producing corresponding clock signals whose frequencies are functions of the magnitudes of the respective correlating signal, without regard to the sign of the respective correlating signal, first counter means responsive to a first one of said up/down command signals and to a first one of said clock signals for producing a first count that is a function of the magnitude of said first correlating signal without any correction applied to said seismic channel, said first up/down command signal and the first correlating signal being associated with said hiline common mode signal, second counter means responsive to the second one of said up/down command signals and to said second correlating signal for producing a second count that is a function of the magnitude of the second correlating signal without any correction applied to said seismic channel, a first multiplying means for multiplying said first count with said hiline common mode signal to produce a first analog correcting signal, a second multiplying means for multiplying said second count with said hiline common mode signal to produce a second analog signal, resistor means for coupling said first correcting signal to a hi one of the two wires of the seismic channel, capacitor means for coupling said second correcting signal to said hi one of the two wires of the seismic channel, substantially identical resistor and capacitor means connected between the lo one of said two wires and ground, said first and second multiplying means operating to produce respective correcting signals that reduce said first and second correlating signals substantially to zero, said first and second counter means retaining respective counts that cause said correcting signals to reduce the correlation between said hiline common mode signal and said hiline differential mode signal to zero and to reduce the correlation between the quadrature phase hiline common mode signal and the hiline differential mode signal to zero.