Single fault tolerant CCIS data link arrangement

Claim 1

In a CCIS data transmission system including first and second switching offices connected via said system, a fault tolerant CCIS data link arrangement comprising: each said switching office including: CPU means; first and second pluralities of terminal equipment connected to said CPU means including respective pluralities of first and second data links for transferring data; said CPU means including: first and second CPUs; a first cable connection from said first plurality of terminal equipment to said first and second CPUs; a second cable connection from said second plurality of terminal equipment to said first and second CPUs; first and second CPU buses corresponding to said first and second CPUs respectively; first and second bus cross-overs corresponding to said first and second CPUs, each cross-over connected to said corresponding CPU via said corresponding CPU bus and to said other CPU via said other CPU bus, for connecting said first CPU to said second CPU bus and for connecting said second CPU to said first CPU bus; corresponding first and second memories connected to each corresponding bus cross-over; corresponding first and second bus extenders connected to each said bus cross-over and to each said memory; and said first and second CPUs being interconnected via said CPU buses and said bus cross-overs whereby said first CPU is active and said second CPU functions as a ready standby or alternatively said second CPU is active and said first CPU functions as a ready standby; each said switching office further including: said first and said second switching offices connected via at least one of said first and one of said second data links; each plurality of said terminal equipment connected to said CPU means and operated to transfer data between said first and second offices; first and second multiplexer units, each multiplexer unit connected to said first and second CPUs via said corresponding CPU buses, each said multiplexer unit operated to connect any one of said pluralities of terminal equipment with said active CPU; first and second registers connected between said first and second CPUs and said corresponding multiplexers and each register operated to selectively enable said active CPU to be connected to specific ones of said pluralities of terminal equipment for transmitting data from any of said pluralities of terminal equipment to said active CPU via said corresponding CPU bus; first and second power generation means corresponding to said first and second pluralities of terminal equipment and each said power generation means operated to provide a plurality of distinct voltage levels to said corresponding plurality of terminal equipment; first and second power buses connected between said first and second pluralities of terminal equipment and said corresponding first and second power generation means respectively, said power buses operated in response to said first and second power generation means to transmit said voltage levels from said first and second power generation means to said first and second pluralities of terminal equipment respectively; said CPU means of said first switching office operated to transfer said data through one of said first and one of second plurality of data links to said second switching office and said CPU means of said second switching office operated to transfer said data through one of said first and one of said second plurality of data links to said first switching office; and said CPU means of each of said switching offices operated to select one of said first data links to transfer all said data between first and second switching offices for a malfunction of said second power generation means or alternatively said CPU means of each of said switching offices operated to select one of said second data links to transfer all said data between said first and second switching offices for a malfunction of said first power generation means.