Method and apparatus for the digital control of the phase of the system clock of a digital signal processing system

Claim 2

Method for digitally controlling the phase of the system clock frequency of a digital signal processing system which processes an analog signal containing a reference signal, wherein a fixed phase relation exists between the reference signal and the system clock frequency, which comprises digitalizing the reference signal by sampling the analog reference signal, weighting the scanning values of the digitalized reference signal for obtaining a digital phase comparison variable, feeding the phase comparison variable through a digital PLL filter to a digitally controlled oscillator, and deriving the system clock frequency from the output signal of the digitally controlled oscillator.

Claim 3

Apparatus for carrying out a method for digitally controlling the phase of the system clock frequency of a digital signal processing system which processes an analog signal containing a reference signal, wherein a fixed phase relation exists between the reference signal and the system clock frequency, comprising an A/D converter for receiving and digitalizing the analog signal containing the reference signal by sampling with a clock signal derived from the system clock frequency, a sampler being connected to and addressed by said A/D converter, a phase comparison circuit connected to said sampler for receiving every n-th sampling value of the reference signal from said sampler during the active time of the reference signal, said comparison circuit determining a phase deviation between the digitalized reference signal and the system clock frequency by weighting, a PLL filter connected to said phase comparison circuit for receiving said phase deviation and providing digital output signals, an oscillator being connected to said PLL filter and being controllable by said digital output signals, said oscillator having an output providing an output signal from which the system clock frequency can be derived.

Claim 4

Apparatus for carrying out a method for digitally controlling the phase of the system clock frequency of a digital signal processing system which processes an analog signal containing a reference signal, wherein a fixed phase relation exists between the reference signal and the system clock frequency, comprising an A/D converter for receiving and digitalizing the analog signal containing the reference signal by sampling with a clock signal derived from the system clock frequency, a sampler being connected to and addressed by said A/D converter, a phase comparison circuit connected to said sampler for receiving every n-th sampling value of the reference signal from said sampler during the active time of the reference signal, said comparison circuit determining a phase deviation between the digitalized reference signal and the system clock frequency by weighting, a PLL filter connected to said phase comparison circuit for receiving said phase deviation and providing digital output signals, an oscillator being connected to said PLL filter and being controllable by said digital output signals, said oscillator having an output providing an output signal from which the system clock frequency can be derived.

Claim 5

Apparatus for synchronizing the system clock frequency of a digital color decoder with the first signal contained in the FBAS signal of a color television receiver containing a burst signal having a given burst time, comprising an A/D converter for receiving and digitalizing the FBAS signal by sampling with n-times the color carrier frequency, a sampler being connected to and addressed by the A/D converter, a phase comparison circuit connected to said sampler for receiving every n-th sampling value of the burst signal from said sampler during the burst time, said comparison circuit determining a phase deviation between the digitalized burst signal and the system clock frequency by weighting, a PLL filter connected to said comparison circuit for receiving the phase deviation and providing digital output signals, and an oscillator being connected to said PLL filter and being controllable by said digital output signals, said oscillator having an output providing an output signal from which the system clock frequency can be derived.

Claim 6

Apparatus for synchronizing the system clock frequency of a digital color decoder with the first signal contained in the FBAS signal of a color television receiver containing a burst signal having a given burst time, comprising an A/D converter for receiving and digitalizing the FBAS signal by sampling with n-times the color carrier frequency, a sampler being connected to and addressed by the A/D converter, a phase comparison circuit connected to said sampler for receiving every n-th sampling value of the burst signal from said sampler during the burst time, said comparison circuit determining a phase deviation between the digitalized burst signal and the system clock frequency by weighting, a PLL filter connected to said comparison circuit for receiving the phase deviation and providing digital output signals, and an oscillator being connected to said PLL filter and being controllable by said digital output signals, said oscillator having an output providing an output signal from which the system clock frequency can be derived.

Claim 7

Apparatus according to claim 3, wherein n=4.

Claim 8

Apparatus according to claim 2, including a digital filter connected between said A/D converter and said sampler acting as a highpass filter for determining the mean position of the reference signal.

Claim 9

Apparatus according to claim 3, including a digital filter connected between said A/D converter and said sampler acting as a highpass filter for determining the mean position of the burst signal.

Claim 10

Apparatus according to claim 2 or 3, wherein said PLL filter is in the form of a proportional integrating filter.

Claim 11

Apparatus according to claim 2 or 3, wherein said PLL filter is constructed in accordance with the filter function: ##EQU6## where z'=e j2 πf/f.sbsp.z and f z is the line frequency.

Claim 12

Apparatus according to claim 2, wherein said phase deviation formed by said comparison circuit is a mean value φ d over sampling values of the reference signal for each n-th line according to: ##EQU7## and for each n (-1)-th line according to: ##EQU8## wherein j=0, 4, 8, . . . .

Claim 13

Apparatus according to claim 3, wherein said phase deviation formed by said comparison circuit is a mean value φ d over sampling values of the burst signal for each n-th line according to: ##EQU9## and for each n (-1)-th line according to: ##EQU10## wherein j=0, 4, 8, . . . .

Claim 14

Apparatus according to claim 2, including means for supplying a color correction value, and including a subtracting stage connected to said sampler, to said phase comparison circuit and to said supplying means, for subtracting said color correction value from sampling values of the reference signal.

Claim 15

Apparatus according to claim 3, including means for supplying a color correction value, and including a subtracting stage connected to said sampler, to said phase comparison circuit and to said supplying means, for subtracting said color correction value from sampling values of the burst signal.

Claim 16

Apparatus for the phase-locked synchronization of the system clock frequency of a device for digitally processing a stereo signal with a pilot tone contained in the stereo signal, comprising an A/D converter for receiving and digitalizing the stereo signal by sampling with n-times the frequency of the pilot tone, a digital filter connected to said A/D converter acting as a bandpass for the frequency of the pilot tone, a sampler being connected to said digital filter and being addressed by said A/D converter through said digital filter, a phase comparison circuit connected to said sampler for receiving every n-th sampling value of the pilot tone, said phase comparison circuit determining a phase deviation between the digitalized pilot tone and the system clock frequency by weighting, a PLL filter connected to said phase comparison circuit for receiving the phase deviation and for providing digital signals, and an oscillator being connected to said PLL filter and being controllable by said digital signals provided by said PLL filter, said oscillator having an output providing output signals from which the system clock frequency can be derived.

Claim 17

Apparatus for the phase-locked synchronization of the system clock frequency of a device for digitally processing a stereo signal with a pilot tone contained in the stereo signal, comprising an A/D converter for receiving and digitalizing the stereo signal by sampling with n-times the frequency of the pilot tone, a digital filter connected to said A/D converter acting as a bandpass for the frequency of the pilot tone, a sampler being connected to said digital filter and being addressed by said A/D converter through said digital filter, a phase comparison circuit connected to said sampler for receiving every n-th sampling value of the pilot tone, said phase comparison circuit determining a phase deviation between the digitalized pilot tone and the system clock frequency by weighting, a PLL filter connected to said phase comparison circuit for receiving the phase deviation and for providing digital signals, and an oscillator being connected to said PLL filter and being controllable by said digital signals provided by said PLL filter, said oscillator having an output providing output signals from which the system clock frequency can be derived.

Claim 18

Apparatus according to claim 13, wherein n=8.