US4524335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse-width modulation circuit with carrier signal frequency control
Assignee: Nippon Gakki Co Ltd
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Filing: 1983-03-10
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Granted: 1985-06-18
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Expires: 2003-03-10
Abstract
Abstract A pulse-width modulation circuit detects a signal level or amplitude of an audio signal by means of an absolute value detecting circuit. The detected level is applied to a control terminal of a voltage-controlled oscillator. The output of the voltage-controlled oscillator is used as a carrier signal of the pulse-width modulation circuit, and the frequency thereof is controlled in such a manner that the carrier frequency is lowered as the audio signal level increases. Higher order harmonics of the pulse-width-modulated output signal both at high and low modulation factors are made substantially the same in amount. Thus, a band width required for the circuit is remarkedly narrowed, and improvement in distortion factor can be attained regardless of a low cost to manufacture.
Inventors
- 👤 Kenji Yokoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:58
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
98 words
A pulse-width modulation circuit comprising: pulse-width modulation means in which a carrier signal is pulse-width-modulated by an input signal to generate a pulse signal having a duty factor corresponding to a level of said input signal; level detecting means for detecting a level corresponding to said level of the input signal; and carrier signal generating means for generating said carrier signal for said pulse-width modulation means, said carrier signal having a frequency which deviates in accordance with the detected level of said level detecting means, the frequency of said carrier signal being decreased as said detected level increases.
Claim 2
Dependent Claim
98 words
A pulse-width modulation circuit comprising: pulse-width modulation means in which a carrier signal is pulse-width-modulated by an input signal to generate a pulse signal having a duty factor corresponding to a level of said input signal; level detecting means for detecting a level corresponding to said level of the input signal; and carrier signal generating means for generating said carrier signal for said pulse-width modulation means, said carrier signal having a frequency which deviates in accordance with the detected level of said level detecting means, the frequency of said carrier signal being decreased as said detected level increases.
Claim 3
Dependent Claim
80 words
A pulse-width modulation circuit as claimed in claim 1, wherein said pulse-width modulation means is comprised of a direct feedback type pulse-width modulation circuit in which said pulse-width-modulated carrier signal is directly fed back to an input side of said circuit; and said carrier signal generating means includes a voltage-controlled oscillator whose output is used as said carrier signal; and wherein an oscillation frequency of said voltage-controlled oscillator deviates in accordance with said detected level of said level detecting means.
Claim 4
Dependent Claim
45 words
A pulse-width modulation circuit as claimed in claim 1 wherein said pulse width modulation means and carrier signal generating means are combined in a self-oscillation type pulse-width modulation circuit having an oscillation frequency which deviates in accordance with said level of said level detecting means.
Claim 5
Dependent Claim
113 words
A pulse-width modulation circuit as claimed in claim 1, wherein said carrier signal generating means comprises: a Miller integrator whose input terminal is supplied with said detected level of said level detecting means; a hysteresis comparator whose input terminal is supplied with an output from said Miller integrator and having a comparator output a fraction of of said comparator output being fed back to said input terminal of said Miller integrator through a resistor; a flip-flop circuit which frequency-divides said comparator output; and an integrator circuit having an input terminal connected to an output of said flip-flop, and an integrator output which is supplied to said pulse-width modulation circuit as said carrier signal.
Claim 6
Dependent Claim
22 words
A pulse-width modulation circuit as claimed in claim 4, further comprising an integration circuit which integrates an output from said flip-flop circuit.
Claim 7
Dependent Claim
26 words
A pulse-width modulation circuit as claimed in claim 1, wherein said pulse signal is demodulated by a low-pass filter and is delivered to a load thereafter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-17 | 1988-12-17 | 1989-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-17 | 1992-12-17 | 1993-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-17 | 1996-12-17 | 1997-06-18 | $7700.00 | Window Closed / Lapsed |