Multi-layer electric circuit board and blanks therefor

Claim 2

A blank for a multi-layer electrical circuit board, comprising an electrically insulating flat substrate having two outer faces and at least one inner layer in said substrate, parallel to said faces and having an electrically conductive network extending throughout the area of said inner layer and formed by the repetition of an elementary predetermined pattern with a predetermined pitch 2p in two orthogonal directions, said predetermined pattern being of such shape that adjacent patterns are in electrical contact and that said inner layer has a first regular grid of predetermined pitch p whose nodes constitute insulated sites and a second grid of pitch p which is off-set by p/2 from the first grid in at least one of said directions, having nodes one at least of which per elementary pattern unit is insulated while the other one belong to the conductive network.

Claim 3

A blank according to claim 1, comprising two of said inner layers, whose grids are off-set by p along one of said orthogonal directions.

Claim 4

A blank according to claim 2, wherein one of said inner layers constitutes a common ground plane and the other one constitutes a common power supply plane.

Claim 5

A blank according to claim 1, wherein each said other sites has an electrically conducting annular zone which defines a central substantially circular aperture having a sufficient diameter for drilling a plated hole connecting said outer faces without contact with the conductive network at said sites.

Claim 6

A blank for a multi-layer electrical circuit board, comprising an electrically insulating flat substrate having two outer faces and at least one inner layer in said substrate, parallel to said faces and having an electrically conductive network extending throughout the area of said inner layer and formed by the repetition of a predetermined elementary pattern in two orthogonal directions, said predetermined elementary pattern comprising three adjacent electrically conductive areas of substantially square outer shape and substantially circular inner shape centered on three out of four nodes of a first square lattice having a pitch, said square outer shape being of such size that adjacent ones of said areas are in mutual electrical contact and define insulating sites between said areas which are distributed at all nodes of a second square lattice of pitch p which is off-set by p/2 from the first lattice in both said directions, said insulating sites being of sufficient size for providing room for conducting holes through said insulating sites without contact with the surrounding ones of said electrically conductive areas.

Claim 7

A blank for a multi-layer electrical circuit board, comprising an electrically insulating flat substrate having two outer faces and at least one inner layer in said substrate, parallel to said faces and having an electrically conductive network extending throughout the area of said inner layer and formed by the repetition of a predetermined elementary pattern in two orthogonal directions, said predetermined elementary pattern comprising three adjacent electrically conductive areas of substantially square outer shape and substantially circular inner shape centered on three out of four nodes of a first square lattice having a pitch, said square outer shape being of such size that adjacent ones of said areas are in mutual electrical contact and define insulating sites between said areas which are distributed at all nodes of a second square lattice of pitch p which is off-set by p/2 from the first lattice in both said directions, said insulating sites being of sufficient size for providing room for conducting holes through said insulating sites without contact with the surrounding ones of said electrically conductive areas.

Claim 8

A blank for a multi-layer electrical circuit board, comprising an electrically insulating flat substrate having two outer faces and at least two inner layers in said substrate, parallel to said faces, each of said inner layers having an electrically conductive network extending throughout the area of said inner layer and formed by the repetition of a predetermined elementary pattern with a predetermined pitch 2p in two orthogonal directions, said predetermined elementary pattern comprising the three adjacent electrically conductive areas of substantially square outer shape and circular inner shape centered on three out of four nodes of a first square lattice having a pitch equal to p, said square outer shape being of such size that adjacent ones of said areas are in mutual electrical contact and define insulating sites between said areas which are distributed at all nodes of a second square lattice of pitch p which is off-set by p/2 from the first lattice in both said directions, said insulating sites being of sufficient size for providing room for conducting holes through said insulating sites without contact with adjacent ones of said electrically conductive areas, wherein the lattices in one of said inner layers are offset with respect to those in the other of said unit layers by p along one of said orthogonal directions.

Claim 9

A blank for a multi-layer electrical circuit board, comprising an electrically insulating flat substrate having two outer faces and at least two inner layers in said substrate, parallel to said faces, each of said inner layers having an electrically conductive network extending throughout the area of said inner layer and formed by the repetition of a predetermined elementary pattern with a predetermined pitch 2p in two orthogonal directions, said predetermined elementary pattern comprising the three adjacent electrically conductive areas of substantially square outer shape and circular inner shape centered on three out of four nodes of a first square lattice having a pitch equal to p, said square outer shape being of such size that adjacent ones of said areas are in mutual electrical contact and define insulating sites between said areas which are distributed at all nodes of a second square lattice of pitch p which is off-set by p/2 from the first lattice in both said directions, said insulating sites being of sufficient size for providing room for conducting holes through said insulating sites without contact with adjacent ones of said electrically conductive areas, wherein the lattices in one of said inner layers are offset with respect to those in the other of said unit layers by p along one of said orthogonal directions.

Claim 10

A blank according to claim 6, wherein each of said electrically conductive areas has an electrically conducting annular zone which defines a substantially cental circular aperture having a sufficient diameter for drilling a plated hole connecting said outer faces without contact with the conductive network.

Claim 11

A blank according to claim 6, wherein each of said electrically conductive areas has an approximately square outer periphery with the sides of the square at 45° from said predetermined directions.