← Back to Patent Explorer
US4523158A Expired / Lapsed US ⏱️ 0.0 years remaining

Clock regenerator using two on-off oscillators

Assignee: RCA Corp
•
Filing: 1983-02-02
•
Granted: 1985-06-11
•
Expires: 2003-02-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A clock pulse regenerator uses a pair of oscillators each comprising a NOR gate and a transmission line feedback element. The oscillators are provided with complementary data pulses and provide an output signal only when the data signal is of a selected logic level. The output signals are combined to form a continuous regenerated clock signal. An FSK encoder using similar oscillators is also disclosed.

Inventors

  • 👤 Mohamed M. A. Megeid

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 02:01
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/24; H04N7/52; H04N7/54; H04N7/56; H04L; H04L27/00; H04L27/10; H04L27/12; H04L7/00; H04L7/02; H04L7/027; H04L7/0276; Y; Y10; Y10S; Y10S331/00; Y10S331/03

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 152 words
Apparatus comprising a first OR gate having a pair of inputs for receiving data signals, and a complementary pair of outputs; a pair of oscillators for producing output signals having substantially the same frequency, each oscillator comprising a NOR gate having a first input coupled to a respective one of said first OR gate outputs, a second input, and an output, and a transmission line coupled between said output and said second input; a second OR gate having a pair of inputs both coupled to one of said first OR gate outputs, and an output for providing delayed data pulses; a third OR gate having a pair of inputs respectively coupled to said NOR gate outputs, and an output for providing regenerated clock pulses; and a transmission line means for delaying said regenerated clock pulses so that the positive going edges thereof occur approximately in the middle of said delayed data pulses.
Claim 2
Dependent Claim 152 words
Apparatus comprising a first OR gate having a pair of inputs for receiving data signals, and a complementary pair of outputs; a pair of oscillators for producing output signals having substantially the same frequency, each oscillator comprising a NOR gate having a first input coupled to a respective one of said first OR gate outputs, a second input, and an output, and a transmission line coupled between said output and said second input; a second OR gate having a pair of inputs both coupled to one of said first OR gate outputs, and an output for providing delayed data pulses; a third OR gate having a pair of inputs respectively coupled to said NOR gate outputs, and an output for providing regenerated clock pulses; and a transmission line means for delaying said regenerated clock pulses so that the positive going edges thereof occur approximately in the middle of said delayed data pulses.

References Cited (Backward Citations)

US2728856A Cited
US3525054A Cited
GB1570207A Cited
US4413236A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-06-10 1988-12-10 1989-06-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-06-10 1992-12-10 1993-06-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-06-10 1996-12-10 1997-06-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag