US4523154A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Enhanced-accuracy semiconductor power amplifier
Assignee: Genrad Inc
•
Filing: 1983-05-18
•
Granted: 1985-06-11
•
Expires: 2003-05-18
Abstract
Abstract A DC amplifier uses complementary npn and pnp output transistors on n-type and p-type substrates, respectively. The output transistors are in an emitter-follower configuration with no emitter resistor to prevent thermal runaway. Instead, emitter-follower driver-stage transistors are provided on the same substrates as the output transistors to force a reduction in the bias voltage on the output stage when the temperature of an output transistor increases. This circuit prevents thermal runaway and temperature-dependent offsets without emitter resistors, which would increase output impedance, and without feedback from the output stage to the input stage, which would slow the response of the amplifier. Additionally, compensation-network transistors are provided to eliminate offsets resulting from driver- and output-transistor base-to-emitter voltage differences caused not only by temperature differences between the transistors on different substrates but also by manufacturing variations. The compensation-network transistors, like the driver-stage transistors, are on the same substrates as the output transistors. They are connected to provide a compensation voltage that is equal to the difference between the base-to-emitter voltages of transistors on the two substrates. The compensation voltage is used to cancel offsets that would otherwise result from such differences.
Inventors
- 👤 James S. Congdon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:24
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/307; H03F3/00; H03F3/30; H03F3/3069; H03F3/3076
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
226 words
A DC electronic amplifier comprising: A. a first semiconductor substrate of n-type semiconductor material; B. a second semiconductor substrate of p-type semiconductor material; C. first and second npn transistors formed on said n-type substrate; D. first and second pnp transistors formed on said p-type substrate; and E. amplifier circuit means interconnecting said first and second transistors of said n-type and p-type substrates as an amplifier in which said second npn and pnp transistors form an output stage in which their emitters are connected together in a complementary emitter-follower configuration for driving an amplifier load connected to said emitters, said first npn and pnp transistors being arranged in a previous stage with their bases connected together in a complementary emitter-follower stage, the emitter of each first transistor on a substrate being coupled to the base of the second transistor on the other substrate so that the sum of the base-to-emitter voltages of said first transistors is applied between the bases of said second transistors, whereby a temperature increase in a second transistor also occurs in the first transistor on the same substrate, reducing its diode drop and thus reducing the voltage impressed across the series combination of said base-emitter junctions of said second transistors, thermal runaway in a second transistor on a substrate thereby being counteracted by the action of the first transistor on the same substrate.
Claim 2
Dependent Claim
226 words
A DC electronic amplifier comprising: A. a first semiconductor substrate of n-type semiconductor material; B. a second semiconductor substrate of p-type semiconductor material; C. first and second npn transistors formed on said n-type substrate; D. first and second pnp transistors formed on said p-type substrate; and E. amplifier circuit means interconnecting said first and second transistors of said n-type and p-type substrates as an amplifier in which said second npn and pnp transistors form an output stage in which their emitters are connected together in a complementary emitter-follower configuration for driving an amplifier load connected to said emitters, said first npn and pnp transistors being arranged in a previous stage with their bases connected together in a complementary emitter-follower stage, the emitter of each first transistor on a substrate being coupled to the base of the second transistor on the other substrate so that the sum of the base-to-emitter voltages of said first transistors is applied between the bases of said second transistors, whereby a temperature increase in a second transistor also occurs in the first transistor on the same substrate, reducing its diode drop and thus reducing the voltage impressed across the series combination of said base-emitter junctions of said second transistors, thermal runaway in a second transistor on a substrate thereby being counteracted by the action of the first transistor on the same substrate.
Claim 3
Dependent Claim
93 words
A DC electronic amplifier as recited in claim 1 further including: A. a third pnp transistor on said p-type substrate; B. a third npn transistor on said n-type substrate; C. compensation circuit means configuring each third transistor with its base-emitter junction forward biased and applying the difference between the base-to-emitter voltages of said third transistors to said amplifier circuit means to subtract the difference voltage from the signals applied to the bases of said second transistors, whereby the difference voltage cancels the difference between the base-to-emitter voltages of the first and second transistors.
Claim 4
Dependent Claim
170 words
A transistor amplifier circuit comprising: A. a unity-gain amplifier including one amplifier transistor or a series combination of more than one amplifier transistor formed on a semiconductor substrate associated therewith, each amplifier transistor being connected in an emitter-follower configuration to form a signal train in which signals appearing at the base of an amplifier transistor are reproduced at the emitter thereof with unity gain but with an offset equal to the base-to-emitter voltage of that amplifier transistor; B. a subtraction circuit, including a reference transistor associated with each amplifier transistor and forward biased to have substantially the same base-to-emitter voltage as its associated amplifier transistor, each reference transistor being formed on the same substrate as its associated amplifier transistor so that its base-to-emitter voltage substantially tracks that of its associated amplifier transistor with changes in temperature, the subtraction circuit being connected to subtract from a voltage in the signal train of the unity-gain amplifier the base-to-emitter voltage of each reference transistor and thereby cancel the offset of each amplifier transistor.
Claim 5
Dependent Claim
170 words
A transistor amplifier circuit comprising: A. a unity-gain amplifier including one amplifier transistor or a series combination of more than one amplifier transistor formed on a semiconductor substrate associated therewith, each amplifier transistor being connected in an emitter-follower configuration to form a signal train in which signals appearing at the base of an amplifier transistor are reproduced at the emitter thereof with unity gain but with an offset equal to the base-to-emitter voltage of that amplifier transistor; B. a subtraction circuit, including a reference transistor associated with each amplifier transistor and forward biased to have substantially the same base-to-emitter voltage as its associated amplifier transistor, each reference transistor being formed on the same substrate as its associated amplifier transistor so that its base-to-emitter voltage substantially tracks that of its associated amplifier transistor with changes in temperature, the subtraction circuit being connected to subtract from a voltage in the signal train of the unity-gain amplifier the base-to-emitter voltage of each reference transistor and thereby cancel the offset of each amplifier transistor.
References Cited (Backward Citations)
JPS5535520A
Cited
US4424493A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-10 | 1988-12-10 | 1989-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-10 | 1992-12-10 | 1993-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-10 | 1996-12-10 | 1997-06-11 | $7700.00 | Window Closed / Lapsed |