PNP comparator circuit having beta current error cancellation

Claim 2

A comparator circuit having first and second inputs and an output, comprising: first and second conductors; first and second transistors of a first conductivity type each having first and second electrodes and a control electrode; said first electrodes being coupled to said first conductor, said second electrodes being coupled to said second conductor, said control electrodes being coupled respectively to the first and second inputs of the comparator; a third transistor of said first conductivity type having first and second electrodes and a control electrode, said first electrode being coupled to said first conductor, said second electrode being coupled to the output of the comparator circuit, said control electrode being coupled to said first electrode of said first transistor; and resistive means coupled between said the second input of the comparator circuit and said control electrode of said second transistor wherein any offset voltage produced due to error current flowing from said third transistor into said first transistor is cancelled.

Claim 3

The comparator circuit of claim 1 including voltage level shifting means coupled between said first electrodes of said first and second transistors and said control electrode of said third transistor for shifting the voltage level therebetween.

Claim 4

A comparator circuit having first and second inputs and an output, comprising: first and second conductors; first and second transistors of a first conductivity type each having first and second electrodes and a control electrode; said second electrodes being coupled to said second conductor, said control electrode of said first transistor being coupled to the first input of the comparator circuit; a third transistor of said first conductivity type having first, second and control electrodes, said first electrode being coupled to said first conductor, said second electrode being coupled to the output of the comparator circuit; voltage level shifting means for shifting the voltage level between said first electrodes of said first and second transistor and said control electrode of said third transistor; resistive means coupled between the second input of the comparator circuit and said control electrode of said second transistor wherein any offset voltage produced due to error current flowing from said third transistor into said first transistor is cancelled; said voltage level shifting means including: (a) diode means coupled between said first electrode of said second transistor and said first conductor; and (b) a fourth transistor of a second conductivity type having first and second electrodes and a control electrode, said first electrode being coupled to said first electrode of said first transistor, said second electrode being coupled to said control electrode of said third transistor and to said first conductor and said control electrode being coupled with said diode means to said first conductor.

Claim 5

A comparator circuit having first and second inputs and an output, comprising: first and second conductors; first and second transistors of a first conductivity type each having first and second electrodes and a control electrode; said second electrodes being coupled to said second conductor, said control electrode of said first transistor being coupled to the first input of the comparator circuit; a third transistor of said first conductivity type having first, second and control electrodes, said first electrode being coupled to said first conductor, said second electrode being coupled to the output of the comparator circuit; voltage level shifting means for shifting the voltage level between said first electrodes of said first and second transistor and said control electrode of said third transistor; resistive means coupled between the second input of the comparator circuit and said control electrode of said second transistor wherein any offset voltage produced due to error current flowing from said third transistor into said first transistor is cancelled; said voltage level shifting means including: (a) diode means coupled between said first electrode of said second transistor and said first conductor; and (b) a fourth transistor of a second conductivity type having first and second electrodes and a control electrode, said first electrode being coupled to said first electrode of said first transistor, said second electrode being coupled to said control electrode of said third transistor and to said first conductor and said control electrode being coupled with said diode means to said first conductor.

Claim 6

The comparator circuit of claim 3 including: first current source means connected between said first conductor and said second electrode of said fourth transistor for sourcing a substantially constant current thereto; and second current source means connected between said first conductor and said diode means and to said control electrode of said fourth transistor for sourcing current thereto.

Claim 7

In a monolithic integrated circuit including a PNP current source transistor having an emitter coupled to a first conductor at which is supplied a source of operating potential, a collector coupled to a load and a base, a comparator circuit, comprising: first and second PNP transistors each having an emitter, a collector and base, said collectors being coupled to a common conductor, said base of said first transistor being coupled to a first input of the comparator at which is applied a first input signal; circuit means coupled between the first conductor and said emitters of said first and second PNP transistors and to the base of the PNP current source transistor for shifting the voltage level between said emitters of said first and second PNP transistors and the base of the PNP current source transistor; and resistive means coupled between said base of said second PNP transistor and a second input of the comparator at which is supplied a second input signal, said resistive means producing an offset voltage that cancels any offset voltage produced by any error current flowing from the base of the PNP current source transistor through said first PNP transistor.

Claim 8

In a monolithic integrated circuit including a PNP current source transistor having an emitter coupled to a first conductor at which is supplied a source of operating potential, a collector coupled to a load and a base, a comparator circuit, comprising: first and second PNP transistors each having an emitter, a collector and base, said collectors being coupled to a common conductor, said base of said first transistor being coupled to a first input of the comparator at which is applied a first input signal; circuit means coupled between the first conductor and said emitters of said first and second PNP transistors and to the base of the PNP current source transistor for shifting the voltage level between said emitters of said first and second PNP transistors and the base of the PNP current source transistor; and resistive means coupled between said base of said second PNP transistor and a second input of the comparator at which is supplied a second input signal, said resistive means producing an offset voltage that cancels any offset voltage produced by any error current flowing from the base of the PNP current source transistor through said first PNP transistor.

Claim 9

The circuit of claim 5 wherein said circuit means includes: a first NPN transistor having an emitter coupled to said emitter of said first PNP transistor, a collector coupled to base of the PNP current source transistor, and a base; and diode means coupled between said base of said first NPN transistor and said emitter of said second PNP transistor.

Claim 10

The circuit of claim 6 including: a first current source connected between the first conductor and said collector of said first NPN transistor; and a second current source connected between the first conductor and said base of said first NPN transistor.

Claim 11

The circuit of claim 7 wherein said diode means is a second NPN transistor having the base and collector interconnected to said base of said first NPN transistor and an emitter connected to said emitter of said second PNP transistor.