Dynamic random access memory

Claim 1

A dynamic random access memory, comprising: a first and second memory arrays, each including a plurality of a word lines (5), a plurality of bit lines (4), and a single dummy word line (6), a plurality of memory cells (1) provided at the intersections between said word lines (5) and said bit lines (4) for writing therein and reading therefrom the data, said memory cells (1) coupled to each word line (5) constituting a column of memory cells, a plurality of dummy cells (3) coupled at the intersections between said dummy word lines (6) and said bit lines (4) for supplying a reference potential, said dummy cells (3) coupled to each said dummy word line (6) constituting a column of dummy cells, a first cell plate (8) coupled to each of said columns of memory cells (1) for supplying a source voltage (+V DD ) to said columns, and a second cell plate (8) coupled to said columns of dummy cells (3) for supplying said source voltage (+V DD ) to said columns, a plurality of sense amplifying circuits (2) each coupled to one end of each said bit line (4) in said first memory array and to one end of each said corresponding bit line (4) in said second memory array for detecting and amplifying a difference between the potential of each said bit line (4) of said first memory array and the potential of each said bit line (4) of said second memory array, word line selecting means (10) coupled to said word lines (5) and said dummy word lines (6) in said first and second memory arrays at one end of each thereof for selecting simultaneously one of said word lines (5) in said first memory array and said dummy word line (6) in said second memory array, bit line selecting means (11, 12) coupled to said bit lines (4) in said first and second memory arrays for simultaneously selecting one of said bit lines (4) in said first memory array and corresponding one out of said bit lines (4) in said second memory array, first cell plate voltage control means (13) coupled to the end of each said word line (5) of said first and second memory arrays opposite to the end where said word line selecting means (10) is connected and also coupled to said first cell plate (8) and being supplied with a control signal (φ G ) having a level changing in a period when said word line (5) is selected and responsive to selection of the word line (5) for bringing the voltage of said first cell plate (8) to a first level and responsive to the change of the level of said control signal (φ G ) for bringing the voltage of said first cell plate (8) to a second level which is different from said first level, and second cell plate voltage control means (13) coupled to the end of each said dummy word line (6) in said first and second memory array opposite to the end where said word line selecting means (10) is connected and also coupled to said second cell plate (8) and being supplied with said control signal (φG) and for controlling the voltage of said second cell plate (8) at the same timing in the same manner as the voltage level of said first cell plate (8) is controlled.