Electronic impedance circuit including a compensation arrangement for d.c. offset
Abstract
Abstract An electronic impedance circuit is constructed of a voltage-current converter and a variable gain current amplifier. The voltage-current converter includes first and second transistors of the PNP-type differentially connected. The variable gain current amplifier includes third and fourth transistors of the NPN-type differentially connected, and fifth and sixth transistors of the PNP-type as load means. The bases of the third and fourth transistors are respectively driven by collector signals of the first and second transistors, and a collector signal of the third transistor is fed back to the base of the second transistor. In order to reduce a d.c. offset attributed to a current flowing between the base of the second transistor and the collector of the third transistor, a compensation circuit is connected to the variable gain amplifier. This compensation circuit can provide compensation by producing a compensation current for cancelling the current between the base of the second transistor and the collector of the third transistor.
Inventors
- 👤 Kazuo Watanabe
- 👤 Yuichi Ohkubo
- 👤 Akira Haeno
- 👤 Fumihiko Yokogawa
Bibliographic Details
Claims Analysis
Total Claims: 1References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |