US4518948A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter
Assignee: US Philips Corp
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Filing: 1982-11-01
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Granted: 1985-05-21
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Expires: 2002-11-01
Abstract
Abstract An analog-to-digital converter incorporating a series arrangement (3, 4, 5, 6) of an integrating circuit (3), a comparison circuit (4), a flip-flop (5) and a gate (6), a clock pulse signal being applied to the two last-mentioned components. An output of the flip-flop (5) is fed back to the input (14) of the integrating circuit (3) to which also the signal to be converted is applied via a switchable current source circuit (15). For effecting an optimum (ideal) integration resulting in a linear conversion, the integrating circuit (3) has a construction as shown in the drawing, it being essential for the product of the value of the capacitor 9 and the resistor 10 to be substantially equal to the value of the capacitor 12 and the resistor 11. The capacitor values and the resistor values may, for example, be equal.
Inventors
- 👤 Frederik J. VanRoessel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:02
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/06; H03M; H03M1/00; H03M1/12; H03M1/60
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
239 words
An analog-to-digital converter incorporating a series arrangement between an input and an output terminal of the converter, comprising an integrating circuit, a comparison circuit, a flip-flop and a coincidence gate, a clock pulse input of the flip-flop and an input of the coincidence gate being connected to a clock pulse input terminal of the converter, the converter incorporating, provided in a feedback path, a switchable current source circuit, a current output terminal of which is connected to an input of the integrating circuit and which is further coupled to the input terminal of the converter, and a current source change-over terminal which is connected to an output of said flip-flop, characterized in that a first input of a differential amplifier incorporated in the integrating circuit is connected to the current source output terminal and to an amplifier output thereof via a series arrangement comprising a first capacitor and a first resistor, a second input being coupled to a terminal carrying a reference voltage and said output of this differential amplifier being coupled, via a series arrangement of a second resistor and a second capacitor, to said terminal carrying a reference voltage, the junction between the second resistor and the second capacitor forming the output of the integrating circuit, and the product of the values of the first capacitor and the first resistor being substantially equal to the product of the values of the second capacitor and the second resistor.
Claim 2
Dependent Claim
239 words
An analog-to-digital converter incorporating a series arrangement between an input and an output terminal of the converter, comprising an integrating circuit, a comparison circuit, a flip-flop and a coincidence gate, a clock pulse input of the flip-flop and an input of the coincidence gate being connected to a clock pulse input terminal of the converter, the converter incorporating, provided in a feedback path, a switchable current source circuit, a current output terminal of which is connected to an input of the integrating circuit and which is further coupled to the input terminal of the converter, and a current source change-over terminal which is connected to an output of said flip-flop, characterized in that a first input of a differential amplifier incorporated in the integrating circuit is connected to the current source output terminal and to an amplifier output thereof via a series arrangement comprising a first capacitor and a first resistor, a second input being coupled to a terminal carrying a reference voltage and said output of this differential amplifier being coupled, via a series arrangement of a second resistor and a second capacitor, to said terminal carrying a reference voltage, the junction between the second resistor and the second capacitor forming the output of the integrating circuit, and the product of the values of the first capacitor and the first resistor being substantially equal to the product of the values of the second capacitor and the second resistor.
Claim 3
Dependent Claim
36 words
An analog-to-digital converter as claimed in claim 1, characterized in that the values of the first capacitor and the first resistor are substantially equal to the values of the second capacitor and the second resistor, respectively.
Claim 4
Dependent Claim
75 words
An analog-to-digital converter as claimed in claim 1, characterized in that in the current source circuit, the current source change-over terminal is coupled to an output of a current source, incorporated in the circuit, via at least one diode, and the current source output terminal is coupled to the output of the current source via at least two diodes which are arranged in series and in the same forward direction as the previously mentioned diode.
Claim 5
Dependent Claim
32 words
An analog-to-digital converter as claimed in claim 3, characterized in that the output of the current source is coupled to said diodes via a series arrangement comprising a coil and a resistor.
Claim 6
Dependent Claim
75 words
An analog-to-digital converter as claimed in claim 2, characterized in that in the current source circuit, the current source change-over terminal is coupled to an output of a current source, incorporated in the circuit, via at least one diode, and the current source output terminal is coupled to the outpt of the current source via at least two diodes which are arranged in series and in the same forward direction as the previously mentioned diode.
Claim 7
Dependent Claim
32 words
An analog-to-digital converter as claimed in claim 5, characterized in that the output of the current source is coupled to said diodes via a series arrangement comprising a coil and a resistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-20 | 1988-11-19 | 1989-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-20 | 1992-11-19 | 1993-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-20 | 1996-11-19 | 1997-05-21 | $7700.00 | Window Closed / Lapsed |